Dear yejf, > but in our VCO as shown bellow there is no ac current source,so how it's equivalent regarding > the impedance that it will present in the actual system? The impedance you are supposed to simulate is the impedance that the inductor will see. The impedance you are computing is from node v_vco to ground. If that is the impedance the inductor will see in your VCO, that is the correct impedance to simulate. > in our varactor there is no "two sides" as in the capactior shown in the schematics bellow. I do not understand how the varactor will vary its capacitance in your VCO circuit as there is no DC isolation of its bottom terminal from its top terminal. You can only change its capacitance with a change in DC voltage across the varactor. You need to include an AC coupling capacitor if you do not have a means to isolate the DC voltage of your varactor bottom terminal. I think you need to study other VCO designs in the literature as it appears your design and the capacitance voltage characteristic you plot need some design effort. Is this a school project or an actual design? This forum is focused on solving Cadence related issues. Shawn![]()
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RE: expression problem from ac sweep
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RE: Deleting PSF data in Simulation
Yes, I am using ADE L. So ADE XL automatically creates a new directory for the data in simulation, while ADE L overwrites every time ?![]()
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Cadence Virtuoso/Design Framework Compatibility with MATLAB
Hello, I would like to use Cadence Design Framework/Virtuoso/Spectre to simulate with MATLAB using cds_srr and the Spectre Matlab Interface. FIrst: 1) How do I install this interfacing function - is their instructions for this ? Second: 2) How do I know they will be compatible. I am using Cadence Virtuoso IC6.1.7 base version for now, with MATLAB 2018. Thank you.![]()
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Orcad Tcl_Create Library Part from Excel File using TCL
Hi Team, Greetings!! I am working to write a tcl code to create the library parts and add the user properties from Excel file(eg., Resistor_olb.xls) Against this Excel File I need to read the cells and create parts then add User properties for that part. Please advise how to achieve this. Also I request you to provide some sample tcl programs regarding this task. Thanks in Advance. Regards, dvk![]()
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How to define a new standard via
I’m trying defining a new via with SKILL.I’ve try using function techCreateStdViaDef to do this but it seems not work.My technology file doesn’t have the new via’s definition and I can not create the via to my cell.Are there any other things I should do or any other functions I should use?By the Way,I’ve also tried defining a new via by modifying my technology file manually and I succeeded,but I still want to succeed with SKILL? Regards John![]()
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RE: How to define a new standard via
Hi![]()
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RE: How to define a new standard via
Hi John, I think we need a little more info about how exactly you make the call to techCreateStdViaDef (..), it's return value and whether you get any errors. There's a lot of things that can go wrong like not having a valid techfile id, specifying invalid layers etc... Max![]()
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Update symbol with added pad
Hello, I'm working with Orcad Professional 17.2. I've a pcb 100% routed. I've to add a hole into a symbol. I edited symbol in library and generated .psm file. If I try to update (with "Update symbol padstack from library") and a error occurs: 'SKIIP' symbol starting to refresh: ERROR(SPMHNI-271): 1 pins found in library symbol, but missing from the symbol in the physical design. They are: 33 Anyone can help me? Thanks Stefano![]()
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RE: Macro Placement in INNOVUS
Thanks.. but now I'm facing another problem.. I want to place physical design of memory macros in another main design.. How to do that??![]()
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RE: Macro Placement in INNOVUS
Thanks.. but now I'm facing another problem.. I want to place physical design of memory macros in another main design.. How to do that??![]()
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Placing of physical design into another physical design in innovus
I want to place physical design of memory macros that I have created separately in another main design in innovus.. How to do that??![]()
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RE: Update symbol with added pad
By the look of it, you haven't added a hole, you have added a Connect Pin. Since the Connect Pins are controlled from the Schematic, you will need to update the Part in the Schematic to Add this Pin and then load an updated netlist to use this footprint. (You will certainly need to do this if you want the added Pin to be connected) IF you don't need the additional Pin to be connected, you can delete the Pin Number Text from the added Pin to change it to a Mechanical Pin (not part of the netlist) and then you will be able to save the changed Package Symbol and update it in the board.![]()
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RE: transient output file option in pspise
No, you get the ".PRINT" to the output file, or the Simulation results from the Probe window. Rather than scratching around with text files, the PSpice Systems Option offers comprehensive integration with MATLAB if that is your aim.![]()
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Breakfast Nibbles: Predictions for 2019
It is the start of the year, so time to provide my predictions for 2019. These are the topics that I expect I will spend a lot of time writing about this year. Let's start with the big picture, and work down to the small (do we call it a 30Å process yet?) Memory Pricing In 2018, the overall semiconductor market was very strong, but much of that was more demand than capacity in the memory market, especially DRAM. With additional capacity coming online, people who follow the memory market full-time all seem to predict softening of prices. For more details, see my post Semiconductor 2018: Up and to the Right...But Memory Way Up . This could mean that the overall headline numbers for the semiconductor market might shrink. From an EDA point of view, it won't matter if the memory market shrinks, since memory companies only do a few designs and then manufacture them in massive volume. I'm always reminded of VLSI's corporate counsel at one point, who had come from Micron, saying in one meeting "At Micron we used to put a couple of designs into production per year, and in the ASIC market we put a couple into production most days." EDA, IP, and generally anything associated with design, is much more driven by the other end markets (see the rest of this post). China With a couple of dozen fabs under construction, this should be the year that some of that capacity starts to come online. But China is the big geopolitical story in many other ways, a big one being that they are committing $150B to semiconductor in a drive to be more self-sufficient. As Chinese fabs come online, even if they are not globally competitive (at least at first) there will be a lot of pressure for Chinese manufacturers to use the chips. Since about half the semiconductors in the world are imported into China, this could have a big effect. It will affect memory first, since China has no competitive leading-edge fabs, but it is worth remembering that a huge percentage of designs are done in non-leading-edge processes. In fact, the #2 foundry GLOBALFOUNDRIES, decided this year not to pursue the leading edge anymore (see my post GTC: GlobalFoundries Pivots ), and China is not pursuing the leading edge anyway (at least for the time being, that could change eventually). I will go to SEMICON China again this year, along with about 90,000 other people based on last year's numbers. So expect more on the Chinese market in late March. 5G This is the year that 5G rollouts will begin. But 2019 will mostly be the year of marketing hype, with pilot projects and expensive handsets that you can't really use anywhere. I expect that this year's Mobile World Congress in Barcelona in March will be an all-out 5G show, with little else being talked about. I won't go into all the details of 5G here, I'll save that for a dedicated post, but 5G is not like previous standards in that there are multiple frequency bands and there is much more of a tradeoff between coverage and performance. I fully expect lots of deliberately planted confusion where the performance of the so-called mmWave band offering speeds of up to 10Gbps gets blurred with the performance of the mid-band and low-band spectrum, which is more like 100+Mbps. The reality is that mmWave won't go through walls, so you won't get that performance from the big basestations, only from so-called small cells. I will be in Barcelona in March, so look for posts on mobile in general and 5G in particular then. EDA in the Cloud Last year the first announcements of EDA in the cloud were made (see, for example, my post Cadence Cloud or my post TSMC OIP Virtual Design Environment) . At ESD Alliance meetings during the year, EDA in the cloud was the big thing that dominated the discussions. So far, it has been a technology using the scalability of the cloud to bring more compute power to bear on the problems. The business models haven't changed, but it wouldn't surprise me to see some tentative changes during the year. Deep Learning, Artificial Intelligence, Neural Networks I use these terms interchangeably. The advances in AI have been truly astounding over the last five or so years. I think that there are two different aspects in which deep learning will affect the semiconductor industry. First, there are all sorts of applications of the technology for end-user applications. I think that training will continue to be largely done in the cloud using GPUs, but that increasingly inference will be done on the edge devices since that is where, in aggregate, most of the compute power is. For my most recent post on this topic, see my post Bagels and Brains: SEMI's Artificial Intelligence Breakfast . Second, deep learning will be increasingly used in EDA tools, both under-the-hood in driving the algorithms inside tools, and also as part of the flow, automating a lot of the iteration that goes on, especially during phases like design closure, synthesis, and physical design. The buzzword here is "no human in the loop." That will remain a dream in 2019, but is certainly the general direction. For more on this topic see my post Cadence is MAGESTIC . Automotive Automotive will continue to be a fast-growing segment of the semiconductor industry, driven by the need for foundries to find markets that are growing as mobile slows or perhaps (in terms of dollars, not transistors) shrinks. It is also driven by the end-markets switching away from human-driven internal combustion engine vehicles owned by individuals to...whatever vision of the world turns out to be true. This is another area where China is leading since, for pollution reasons, they are basically making it increasingly hard to purchase anything other than electric vehicles. For more on this, see all the links in yesterday's post in the automotive section. Processes: EUV, 5nm, 3nm In 2019, 7nm (and Intel's 10nm which is similar) will be mainstream. EUV will be in true volume production. The bleeding edge of process development will move to 5nm. Just because EUV works at 7nm doesn't mean that there are not major issues for 5nm. As was said at SEMICON West last year, "we're gonna need more photons." Next-generation interconnect might well be based on ruthenium (Ru). At 3nm, it looks like transistors will be nanosheet gate-all-around (GAA). For more on this area, see my posts from the recent IEDM (some of which have appeared, and some of which will appear in the next couple of weeks). Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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RE: Update symbol with added pad
Solved. Sorry but I'm newbie :-) Thank you very much Stefano![]()
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RE: Deleting PSF data in Simulation
Yes, although ADE XL (Options->Save) does allow you to control how many history points are kept, or whether you want it to just keep overwriting. ADE L does have some capability to write into new results directory each time (e.g. when using distributed processing), but in general it overwrites the results each time. Andrew![]()
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RE: add_ignore_pins create_ccopt_clock_tree_spec
Hi Chetan, I have read these articles, good ones. But this does not answer this question. I have the same message and I want to understand why CCopt is modifying the native spec file to add ignore pins to a skew group. Regards, Hatem![]()
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RE: Cadence Virtuoso/Design Framework Compatibility with MATLAB
The "cds_srr" interface is supported from the SPECTRE stream (historically the MMSIM stream). You can find info on it by running /bin/cdnshelp and then searching for "matlab". There is a support matrix but doesn't look as if anyone has maintained it for some time... anyway, I regularly use Matlab 2018a and 2018b and they should work OK. However, if using ADE Explorer and Assembler, there's a newer, tighter integration. This is shown in these two videos: Using the Enhancement Virtuoso ADE Product Suite and MATLAB Integration: A Practical Guide (a recent-ish joint video with the MathWorks) Making the most of using MathWorks MATLAB and Virtuoso ADE Product Suite together (a shorter introductory video from 2017) Both have a mixture of presentations demos (and both have me talking... so apologies in advance) There's a Rapid Adoption Kit (under Resources on the support site) for this too. This integration makes it much easier to use Matlab expressions in ADE, whereas the cds_srr interface is a lower level interface to the results reader (the new interface is built on top of cds_srr, but it provides lot of higher level functions for interfacing to ADE). Regards, Andrew.![]()
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RE: Cadence Virtuoso/Design Framework Compatibility with MATLAB
Hello, Thank you for your response. By MMSIM stream, do you mean Spectre Virtuoso/Cadence version IC5.x or IC6.1.6 and previous ? By ADE Explorer and Assember, do you mean Spectre Virtuoso/Cadence version IC6.1.7 and above ? Or do you mean something else ? Thank you.![]()
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RE: Migrating CIS from 16.5 to 17.2 -- 32-bit vs. 64 bit?
Whew! Thank you. I just upgraded CIS to 17.2 and got stuck. Your solution was perfect.![]()
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