[quote userid="383860" url="~/cadence_technology_forums/f/rf-design/40910/expression-problem-from-ac-sweep/1358415#1358415"]If you are trying to measure the current through your entire varactor network, the current probe can be placed in series with the gate of the drain-source connected MOS device. Remove the 100K resistor totally. The probe will then capture all the current through the drain-source connected device and the switched capacitors.[/quote] Hello i have changed the circuit and the simulation as you said with the expression shown bellow. i added a 1A ac source and 1mH inductor in series with the VVDC source. in the results of the formula it gives a constant capacitance no matter what VVDC voltage . where in the AC current source did i got wrong? another problem is why we dont calculate the capacitance from the OUT node signed in red? the VCO will look at the capacitance from that point,so we do need to put the iprobe there and VOUT there am i correct? Thanks (-1 / (2 * 1e+09 * value(imag(v("/vout" ?result "ac") / i("/IPRB0/PLUS" ?result "ac")) 1e+09) * pi))![]()
↧
RE: expression problem from ac sweep
↧
RE: layout instances name connected in a selected net.
Hi Andrew! Is there any way to obtain the devices connected on a net from the schematic view?![]()
↧
↧
RE: layout instances name connected in a selected net.
[quote userid="415245" url="~/cadence_technology_forums/f/custom-ic-skill/14672/layout-instances-name-connected-in-a-selected-net/1358429#1358429"]Is there any way to obtain the devices connected on a net from the schematic view?[/quote] Please read the Forum Guidelines . You've asked a question in a 9 year old thread which is about layout instances, and you're asking about instances on a schematic. So that's at least two of the forum guidelines broken. I suggest you start a new post.![]()
↧
RE: layout instances name connected in a selected net.
Hi Sttrotta, Something like these. /*============================================================================================================ Purpose : Displays devices lists that are connected in a selected net or wire in the schematic and higlights all its connection. It can be use for tracing connections in schematic. Process : Any process Environment : VXL schematic editor , this skill file can also be run in VXL layout editor. How to run : 1.Enter in CIW. load("/home/marben/SKILL_VXL/net_selected.il") 2.Select a portion of net or wire in the schematic window, then move the cursor in the CIW, then press 2 in the keyboard. 3.All devices connected to that net will be automatically displayed in a text file, netConnection_layout.txt will be automatically created in user's VXl directory. Function Name : net_selected() Language : SKILL Date created : February 17, 2010 Author : Marben F. Orallo =============================================================================================================*/ ;hiSetBindKey("Command Interpreter" " 2" "net_selected() ") hiSetBindKey("Layout" " 2" "net_selected()") hiSetBindKey("Schematics" " 2" "net_selected()" ) procedure(select_side() foreach(fig geGetSelSet() net=fig~>net ) foreach(fig net~>figs geSelectFig(fig)) ) procedure(net_selected() csh("touch ./netConnection_layout.txt") outPort = outfile("./netConnection_layout.txt") foreach(fig geGetSelSet() net=fig~>net when(net printf("net %s is connected to\n" net~>name) foreach(instTerm net~>instTerms printf("%s.%s " instTerm~>inst~>name instTerm~>name) ) printf("\n") ) fprintf(outPort " Net %s schematic connection are :\n\n" net~>name ) ;fprintf(outPort "net %s is connected to\n" net~>name) foreach(fig geGetSelSet() net=fig~>net when(net foreach(instTerm net~>instTerms fprintf(outPort " Pin %s of instance name %s , cellname = %s \n" instTerm~>name instTerm~>inst~>name instTerm~>inst~>cellName) ) ) ) ) ; start of outport fprintf(outPort " \n\n\n >>" ) fprintf(outPort " \n\n End of schematic net connection list . " ) fprintf(outPort " \n\n >>" ) close( outPort) ;view("./netConnection_layout.txt" list(0:0 500:500) "SCHEMATIC NET CONNECTION") ; edit("./netConnection_layout.txt") ;hiRegTimer("system("open_net_selected")" 100) sleep(3) system("gedit netConnection_layout.txt &") ; End of outport select_side() )![]()
↧
RE: expression problem from ac sweep
Dear Yefl, > in the results of the formula it gives a constant capacitance no matter what VVDC voltage . > where in the AC current source did i got wrong ? You did not set the DC potential at your top node vout to be anything. Hence, it is floating and will take on the same value as your applied control voltage (vvdc). Hence, there will be no change in capacitance as you change the control voltage vvdc. > another problem is why we dont calculate the capacitance from the OUT node signed in red? > the VCO will look at the capacitance from that point,so we do need to put the iprobe there and VOUT there > am i correct? I was wondering where the VCO node was. Please use the circuit shown in the attached file to measure the capacitance as a function of your control voltage: Shawn![]()
↧
↧
RE: iPad files manager
you have to Jairbreak to do that Regards, Lisa![]()
↧
RE: transient output file option in pspise
I include a file and it works but data has been written into output file. Is there any way to write data into a separate file? because when I want to use this data in MATLAB or another application, output file has other information too, that I don't need them and it became a little hard to work.![]()
↧
RE: ncsim: Error within protected source code.
It is not possible to ncsim error within the protected source code and you can follow some good methods to do it with the help of third-party applications which are rolled out by McAfee Customer Service Hope this helps you out with your queries.![]()
↧
RE: expression problem from ac sweep
Hello , i have made the test bench as you described and i got results. but in our VCO as shown bellow there is no ac current source,so how it's equivalent regarding the impedance that it will present in the actual system? another thing is how do you suggest connecting it to the VCO? in our varactor there is no "two sides" as in the capactior shown in the schematics bellow. Thanks.![]()
↧
↧
RE: Voltus-Fi XL in ADE with dspf: how to reliably start 'shapeSever'
Cadence Support Troubleshooting article: VoltusFi : Failed to start QRC module 'shapeServer'![]()
↧
QRC Assura Extraction failing !
Hi I'm trying to run parasitic extraction on Assura QRC, and the run is failing. The log file says that it couldn't get the library models for the NMOS, PMOS. Something like this: My setup is as follows: Can someone tell me what's going wrong? Andrew Beckett Tawna ?![]()
↧
RE: QRC Assura Extraction failing !
Hi Aalhad You had encountered a licensing error as indicated in the log file. Quantus XL license is required for the extraction but the license is not available. Best regards Quek![]()
↧
Sunday Brunch Video for 8th January 2019
https://youtu.be/tAMYvJJcPy0 Made at Vieira Park, San Jose (camera Carey Guo) Wednesday: 150th Anniversary of the Periodic Table of the Elements Thursday: IEDM: The World After Copper Friday: RISC-V Cores: SweRV and ET-Maxion www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
↧
↧
Looking for a job in Netherlands
Hi everyone, I am Han Saman Lissa, I am 32 and I have experience 3 year at webdesign, and almost 1 year at data recover. I want to find a job in Netherland, where ever thank you![]()
↧
RE: embedded telemetry receiver
follow the fieldengineer for freelance opportunities. What is Field Engineer A Global Marketplace connecting Engineers and Businesses No matter where you are in the world, FE is connecting engineers and telecoms every day. Nowhere is too far away - and even remote jobs can be handled easily through our global platform. Field Engineer is an online marketplace that connects companies with telecommunications work with the global field engineers who have the skills and availability to complete them. With more than 40,000 skilled field engineers in 170 countries, Field Engineer has already helped 45 service providers get jobs done.![]()
↧
RE: SKILL code to print all the labels in a layout view to a file
Hi Andrew, In the above script, is there a way to find the coordinate location of a label? Thanks, Mallikarjun![]()
↧
RE: SKILL code to print all the labels in a layout view to a file
Hi Mallikarjun, It's not my code, but you could use shape~>xy to find the coordinate (origin) of the label. Regards, Andrew.![]()
↧
↧
2018: A Year of Breakfasts
It's the start of a new year. Tomorrow, I'll pick out what I think that the big trends for 2019 are going to be. But today, let's take a look at how my predictions for 2018 fared from my post Nibbles: Breakfast Bytes Predictions for 2018 . You can make your own judgment about whether I missed something, but one good measure of whether I picked the right topics, is simply how much I wrote about them in the (roughly) 250 posts that appeared during 2018. Security I picked security of being one of the big trends for 2018. To be honest, I cheated since my prediction post came out a couple of weeks into the year. But 2018 started with a story so big that I wrote a second Breakfast Bytes post that day, January 3, What is Meltdown? How Can It Affect Both Intel and Arm? about the Spectre and Meltdown vulnerabilities that had been hiding in plain sight for 15 or 20 years. There was a great panel session about it later in the year, during HOT CHIPS, that I covered in three posts Spectre/Meltdown and What It Means for Future Design 1 , 2 , 3 . Those 3 posts contain a more thoughtful perspective than the post that I wrote in the afternoon of the day I found out about the vulnerabilities. But these weren't the only security stories of the year. The second time I wrote another Breakfast Bytes post on the same day was also security related. Bloomberg published a story about how Amazon, Apple, and others had extra chips added to their servers by the Chinese. It seemed bogus to me. Bloomberg still hasn't retracted the piece, but everyone who has written about it says that it is false. The pieces was Did the Chinese Really Attach Rogue Chips to Apple and Amazon's Motherboards? Why You Shouldn't Trust Ken Thompson Passwords: How Even Your Bank Doesn't Know Your PIN Passwords: Just Add Salt Fooling Neural Networks Spectre with a Red Hat A Computer Scientist Takes a Look at Mechanical Security RSA Cryptographers' Panel Some Real Russian Hacking Compromising a Fortune 500 Company...Without Hacking a Thing RSA Wrapup: Song, Darling, Thrun Spectre/Meltdown and What It Means for Future Design 1 , 2 , 3 . ERI: Hardware Security Workshop Google's Titan: How They Stop You Slipping a Bogus Server into Their Datacenter Did the Chinese Really Attach Rogue Chips to Apple and Amazon's Motherboards? Autonomous Cars Automotive is the fastest growing segment of the semiconductor industry. The whole industry is in transition, driven by the move to electric traction, the move towards autonomous driving, millennials owning cars in much lower numbers, and more. Cadence held its first Automotive Summit in November. CES Keynotes: Cars, Flying Cars, Dancers, Music, Lights...and Sustainability In Other News, 100 People Were Killed by Cars Driven by People CDNLive EMEA, Driving to the Future CDNDrive: ISO 26262...Chapter 11 Legato: Smooth Reliability for Automobiles Automobil Elektronik Kongress 2018 Trends, Technologies, and Regulations in China's Auto Market CDNDrive Automotive Solutions: the Front Wheels CDNDrive Automotive Solutions: the Rear Wheels Texas Instruments on Automotive Reliability Automotive Summit: The Road to an Autonomous Future Automotive Sensors: Cameras, Lidar, Radar, Thermal Artificial Intelligence AI, deep learning, neural networks—the biggest change in how we program goes under a lot of names. Linley: Training in the Datacenter, Inference at the Edge Deep Blue, AlphaGo, and AlphaZero SEMICON West: The AI Tectonic Shift Accelerating AI: Past.. . ...Present and Future Embedded Vision: Seeing 20,000X Improvement Overcoming Bias in Computer Vision Cadence Is MAGESTIC HOT CHIPS Tutorial: On-Device Inference HOT CHIPS: Some HOT Deep Learning Processors David White and Machine Learning The New Tensilica DNA 100 Deep Neural-network Accelerator Inside Google's TPU and Google TPU Software Bagels and Brains: SEMI's Artificial Intelligence Breakfast Neural Nets Hit the Roofline—Memory for AI 5nm With 7nm in production, 5nm is the "next" process. In some ways, I should have combined this with the next topic EUV, since 5nm requires EUV. Everyone's approach to insertion of EUV is to do a second generation of 7nm with some EUV layers for cost-reduction, to build up experience, and potentially slightly tighter pitches. Then, for 5nm, use EUV from the start. IEDM Short Course: After 5nm 3nm Cadence and imec TSMC Technology Symposium 2018 Samsung Foundry Forum: 10, 8, 7, EUV, 5, 4, GAA, 3... How Low Can You Go? TSMC OIP Ecosystem Forum EUV By definition, most of the above posts about 5nm are also, at least partly, about EUV. But there were other times I wrote about EUV more directly. GLOBALFOUNDRIES 7nm If It's Tuesday This Must Be Belgium. My First Visit to imec Imec on EUV. Are We There Yet? SEMICON 5nm: 7nm Is Just a Dress-Rehearsal China Apart from my post about China inserting (or rather not inserting) chips on everyone's server farm motherboards (see under security above), and my pieces on automotive in China (see under Automotive above), I also covered the Chinese semiconductor industry more directly. I also came across a great word for people who know very little about China thinking that they can explain it. So maybe I'm guilty of Hansplaining here. SEMICON China: Me and 70,000 of My Closest Friends SEMICON China: Is This China's Decade? The Great Firewall of China China Update The Economist on Silicon Supremacy Photonics One area that I didn't call out as a prediction was silicon photonics, which I think was a significant omission. Cadence had its first Silicon Photonics Summit this year, and a workshop on the second day (with Lumerical and Mathworks). Yoga is Passé, the Future Is CurvyCore Diwali, the Hindu Festival of Lights...and Photonics, the Silicon Festival of Light An Illuminating Chat with Lumerical's CTO Predictions for 2019 Tomorrow, my predictions for the major themes for 2019. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
↧
RE: Suppress: *WARNING* COMBINE attribute library not defined
Hi Andrew, I found what caused the warnings. However the possibility to suppress them would be useful. Thank you Best regards, Aldo![]()
↧
RE: Problem about font
Thanks Steve. I traied to change the fonts in Options - Design Template, but I don't fix the problem.![]()
↧
