I added some code around it so that I could debug the problem. The issue was in this line: arrayGenForm->arrayGenTopFrame->summaryLayout->iconLabel-> labelIcon =icon It should have been: arrayGenForm->arrayGenTopFrame->summaryLayout->iconLabel-> value =icon Here's the modified code (with the additional fields to help me debug): dl=dlMakeDisplayList() penTable=dlMakePenTable(5) dlSetPenTable(dl penTable) colorIndex=hiMatchColor(nameToColor("red")) dlSetPenColor(1 colorIndex penTable) dlSetPenFillStyle( 1 "SolidFill" penTable) dlAddBox(dl 1 list(0 0) list(200 200) 'bigBox) dlAddBox(dl 4 list(20 20) list(180 180) 'littleBox) /* just checking what the icon would have looked like let(((w 50) (h 30)) dlClearDisplayList(dl) dlAddBox(dl 1 list(0 0) list(round(w) round(h)) 'extentBox) ) */ icon=dlDlistToIcon(dl 200 200) enterLayout=hiCreateHorizontalBoxLayout('enterLayout ?frame "Debug" ?margins list(50 20 50 20) ?spacing 50 ?items list( hiCreateFloatField( ?name 'width ?prompt "Width:" ) hiCreateFloatField( ?name 'height ?prompt "Height:" ) hiCreateButton( ?name 'updateIt ?buttonText "Update" ?callback "updateIcon()" ) ) ) summaryLayout=hiCreateHorizontalBoxLayout('summaryLayout ?frame "Summary" ?margins list(50 20 50 20) ?spacing 50 ?items list( hiCreateFloatField( ?name 'totalWidth ?prompt "Total Width:" ?editable 'nil ) hiCreateFloatField( ?name 'totalHeight ?prompt "Total Height:" ?editable 'nil ) hiCreateLabel( ?name 'iconLabel ?labelIcon icon ) ) ) sep1=hiCreateSeparatorField(?name 'sep1) sep2=hiCreateSeparatorField(?name 'sep2) arrayGenTopFrame=hiCreateFormLayout('arrayGenTopFrame ?frame "Top Frame" ;?items list(coreLayout sep1 ewLayout nsLayout cornerLayout sep2 summaryLayout) ?items list(sep1 enterLayout sep2 summaryLayout) ) hiCreateLayoutForm('arrayGenForm "arrayGen Compound Array Generator" arrayGenTopFrame ?callback 'arrayGenFormCB ?minSize 800:10 ) procedure(coreLCVCB() size=getCellSize( arrayGenForm->arrayGenTopFrame->coreLayout->coreLCVLayout->coreL->value arrayGenForm->arrayGenTopFrame->coreLayout->coreLCVLayout->coreC->value arrayGenForm->arrayGenTopFrame->coreLayout->coreLCVLayout->coreV->value ) arrayGenForm->arrayGenTopFrame->coreLayout->coreWidthLayout->coreCellWidth->value=car(size) arrayGenForm->arrayGenTopFrame->coreLayout->coreHeightLayout->coreCellHeight->value=cadr(size) ddsUpdateSyncWithForm() updateIcon() ) procedure(updateIcon() let((lib cell view file w h icon) /* lib=arrayGenForm->arrayGenTopFrame->coreLayout->coreLCVLayout->coreL->value cell=arrayGenForm->arrayGenTopFrame->coreLayout->coreLCVLayout->coreC->value view=arrayGenForm->arrayGenTopFrame->coreLayout->coreLCVLayout->coreV->value w=arrayGenForm->arrayGenTopFrame->coreLayout->coreWidthLayout->coreTotalWidth->value h=arrayGenForm->arrayGenTopFrame->coreLayout->coreHeightLayout->coreTotalHeight->value */ w=arrayGenForm->width->value h=arrayGenForm->height->value ; method 1: this does not work - the image stays blank regardless of cell selection dlClearDisplayList(dl) dlAddBox(dl 1 list(0 0) list(round(w) round(h)) 'extentBox) icon=dlDlistToIcon(dl 200 200) printf("setting icon: %L w=%L h=%L\n" icon w h) ; THIS LINE WAS INCORRECT... ;arrayGenForm->arrayGenTopFrame->summaryLayout->iconLabel->labelIcon=icon arrayGenForm->arrayGenTopFrame->summaryLayout->iconLabel->value=icon ; method 2: this works - the image is refreshed every time you select a different cell ; whether you use hiLoadIconFile or hiLoadImageFile ; file=ddGetObj(lib cell view hiGetThumbnailFilename())->readPath ; when(file ; icon=hiLoadIconFile(file 200 200) ; printf("setting icon: %L\n" icon) ; arrayGenForm->arrayGenTopFrame->summaryLayout->iconLabel->value=icon ; ) ) ) ; to test ; hiDisplayForm(arrayGenForm) When initially displaying the form, it appears like this (so the display list icon is clearly being used): If I enter some values in the Debug fields and hit Update, the form updates: Here's a second update: So I think it's just down to the statement above. I didn't quite get what you meant about "just a black box" - for me before this tweak to the code, the icon remained as it did initially (the first image above). Merry Christmas and a Happy New Year! Regards, Andrew.![]()
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RE: dlDlistToIcon result is not usable in a form
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RE: How to change or set connection information for a MOS in layout XL?
Hi Andrew, The function is called _lxMakeDummy(“netName”). And In layout XL, you can select a mos -> click right-mouse-button -> click Create Dummy With Net -> click a net name -> point reference point in layout window -> point location in layout window. You can test this as I said above. My virtuoso version is IC617 ISR15 Regards, Dave![]()
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RE: How to change or set connection information for a MOS in layout XL?
Hi Dave, I know how to do this, thanks. As I said though, there's no public function (the function you mention is the one triggered by the menu, which I was already aware of, and it's private and not intended for use in SKILL code). You'd need to contact customer support as I mentioned earlier if you want an enhancement for a procedural interface to do what you want (i.e. without needing interactive input). Regards, Andrew.![]()
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RE: How to change or set connection information for a MOS in layout XL?
OK，Thanks for your suggestion. Regards, Dave![]()
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I'd like to use the keyboard's "Enter" as a stroke or short key in pcb editor.
hello. I have a question. Please reply. I'd like to use the keyboard's "Enter" as a stroke or short key in pcb editor. I can't find a way. Don't you support it on PCB editor? If there is any other way, please let me know. thank you.![]()
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RE: Can not open more then one board design in 17.2
Is it possible selecting some objects in the viewer and then past in the other PCB?![]()
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RE: Can not open more then one board design in 17.2
Thank you for your support. I have some annoying problem which is funckey functions are lost if I click on any menu item. If I click to menu tabs or something on visibility, find and options tabs, function keys don^t work anymore. I need to click to the area which is next to green bar under the command window and then funckeys start working again. I need to click that area everytime I make some changes on that visibility, options or find tabs. Is that a common issue or something wrong with my scripts or env file? With kind regards, Ahmet![]()
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Patterns, a Unified Language between Design and Manufacturing
There will be no design without manufacturing and manufacturing is mainly about patterns and patterning. Without proper transfer of the design patterns to silicon, there would be no semiconductor product. So, it’s with no surprise that several papers on pattern analysis have been selected in the DTCO session of the SPIE Advanced Lithography conference. In this session, you will find 3 papers, co-authored with Cadence, which cover a wide range of applications based on advanced pattern analysis. I find it interesting that each of these papers covers one essential step of the design to manufacturing flow: design signoff, mask data preparation and failure analysis. The first paper is about hotspot prediction at signoff. In collaboration with the Hong-Kong University, Cadence will present a yield improvement application based on Squish-net, the new Cadence machine learning solution dedicated to pattern analysis. Unlike other hotspot prediction based on machine learning which suffer from inefficient data storage (e.g. images), or information loss (e.g. density-based feature, and CCS), Squish-Net is a convolutional neural network where the input pattern is encoded in squish representation, resulting in high data compression with no information loss. In this flow, the machine learning prediction stage is combined with the pattern cataloging and pattern matching steps for full-chip level layout verification and demonstrated a 98.89% accuracy in predicting hotspot labeled patterns on the ICCAD 2012 benchmark. For more information about this collaboration, attend this session “ Hotspot Detection Using Squish-Net ” on Thursday, Feb. 28. 1:30 – 3:30 Strong from their past collaboration on machine-learning based hotspot prediction, Cadence and Samsung teamed up again to address, this time, the fixing of these hotspots and the general improvement of layout quality prior to mask data prep. A full-chip pattern-based layout optimization to improve the robustness and process window of weak spots and add via redundancy prior to mask data prep. This solution applied to 7nm designs achieved 9.1%-41% redundant-via-rate improvements. This pattern-based replacement for design manufacturability improvement is also based on the squish representation. It is applied prior to mask data preparation but can be easily extended to in-design layout optimization. For more information about this collaboration, attend this session “ A Novel Design-for-Yield Solution Based on Interconnect-Level Layout Improvements at 7nm Technology Node ” on Wednesday, Feb. 27. 8:00 a.m. – 10:00 a.m. Despite all the effort to predict and prevent hotspots, failures may still happen and root cause analysis (RCA) is very time-consuming and costly. AMD will present a pattern-aware diagnostics solution to accelerate defect root cause identification developed with Cadence. Using the high-performance Cadence pattern cataloging and powerful Squish representation, a library of scored patterns from multiple established full-chip designs is built and then compared to the patterns interacting with nets reported in diagnosis callouts. All these patterns of interest (POIs) are then further analyzed to identify the features of interest (FOIs), augmented with the volume diagnosis results identifying nets with likely open or short defects, and exported as a dataframe. This dataframe is then processed by conventional machine learning techniques to identify likely root cause(s) for failures and suggest refined failure locations for targeted inspection, physical failure analysis, or other electrical failure analysis. For more information about this solution, attend the session “ Pattern-Aware Diagnostics: Using High-Performance Pattern Analysis to Identify Defect Root Cause ” on Wednesday, Feb. 27. 10:30 a.m. – 12:10 p.m. Please join us at SPIE for these exciting presentations and learn more about Cadence DFM and lithography solutions February 26 and 27 at booth 213 in Exhibition Hall 1. Cadence will also hold private customer meetings. Check out our event page to learn more and register today by visiting the SPIE Advanced Lithography website. We hope to see you in San Jose for SPIE Advanced Lithography's 44th year!![]()
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PSpice Co-Simulation ERROR(ORPSIM-2604): PSpice returned error. Terminating simulation.
Hello, in SLPS CoSim, while simulating the demo files I am getting the error as shown below. please help to resolve this error OrCAD version:17.2 hotfix : 049 MATLAB version r2017a thanks, Jesh![]()
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Silent Night
Happy Christmas from Breakfast Bytes. It's Christmas Eve 2018, and 200 years ago today, Christmas Eve 1818, was the first performance of Silent Night, although since this was Oberndorf, Austria, it was in German, Stille Nacht . You may know the story. The church organist discovers that the organ bellows have been destroyed by mice, so there will be no organ for the Christmas Eve service. So he dashes off a quick carol to be sung accompanied by a guitar, and it is an instant hit. Indeed, Bing Crosby's 1935 version is the 3rd best-selling single of all time. There's something about Bing and Christmas music since White Christmas is still the number 1 best selling single of all time. Between them is Elton John's version of Candle in the Wind from Princess Diana's funeral. Fourth is Rock Around the Clock . Actually, almost none of that story is true. For a start, the lyrics and the music were not created by the same person. The lyrics were created a couple of years earlier where the parish priest, Joseph Mohr, in Oberndorf had had his previous job. The melody was by Franz Xaver Gruber, who was an organist, but in a nearby village. But the part about the organ being damaged is true, although by flooding, not church mice. So Mohr got Gruber to put together a melody and guitar accompaniment to be used that night. Surprisingly, some of the true story only came to light in 1995. Until then it was assumed that Gruber wrote the words too. But the (or at least an old) original manuscript of the carol was discovered in 1995, in Mohr's handwriting. Here's a fact you probably don't know. The original lyrics (in German) have six verses. In English, only the first, second, and sixth were translated, by John Freeman Young of Trinity Church in New York. Those are the words sung today in the English-speaking world. The other verses are more to do with the end of the Napoleonic Wars, and not the nativity. That church didn't seem to be very well sited, since it was eventually destroyed by flooding. Now there is the Silent Night Chapel on the spot, I've never visited, but from the picture there are a lot of steps in front of the chapel, presumably to keep it out of floodwater. Or perhaps the river has been controlled by other means. A famous performance was by the German and British troops on Christmas Eve 1914, although performance is probably not the right word. One tune, two sets of lyrics. They then famously came out of the trenches and exchanged gifts that first Christmas Eve of the First World War. Wikipedia tells me that Silent Night has been an Intangible Cultural Heritage since 2011, which seems to mean that it is like a Unesco Heritage Site but you can't visit it. Luckily, too, you can't do much to stop it being passed through the generations if people want to, unlike Palmyra in Syria, or Buddhas of Bamiyan. People will still be singing Silent Night for a long time. Silent night, holy night! All is calm, all is bright Round yon Virgin, Mother and Child Holy Infant so tender and mild Sleep in heavenly peace Sleep in heavenly peace Happy New Year Breakfast Bytes will be back on January 2nd with another anniversary, it is the 150th anniversary of The Periodic Table of the Elements, something of more significance to semiconductors. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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17.2HF049 capture part editor,move text/pin number/pin name can't snap to grid
17.2HF049 capture part editor,move text pin number/pin name can't snap to grid and pin number/pin name can’t restore default location![]()
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Renesas Brings Their Legacy Testbench Up to Speed Using the Cadence Verification Suite
Recently, Renesas Electronics Corporation faced a challenge. They were developing a new data conversion block, one that included an AHB bus bridge, which would be attached to a pre-existing DMA IP core. There was also a complicated finite state machine involved in this new block. Renesas didn’t have a whole lot of time on their hands—they needed a quick turnaround time, but only had a limited amount of engineers to accomplish that with. Because of that, they wanted to recycle a few in-house IPs and the verification of those IPs in their new project, despite having a team that wasn’t involved in those previous endeavors. Beyond that, Renesas also wanted to upgrade their verification methods with top-of-the-line tech. They wanted this verification environment to be a model which other IP core design projects could follow. Quite a tall order—but it was easy with Cadence’s help. Using Cadence tools and assistance from Cadence application engineers, Renesas was able to use Specman e ’s native scalability to keep their old legacy testbench, even though there were over 45 component files and loads of internal connections across different components. After that, Renesas used the Cadence Xcelium Parallel Logic Simulator alongside the Cadence Indago Debug Analyzer App, taking advantage of the e language to help them build complex and scalable testbenches. “To make the best use of the existing IP cores, renewing the legacy verification environment with the most advanced tools available proved to be an effective approach. Positive and collaborative relationships with Cadence played a key role to achieve it,” said Takahiro Ikenobe, director of the peripheral circuit design department at Renesas Electronics. Using Cadence products gave Renesas a 77% savings in labor while still meeting Renesas’s standard of high quality. With the vManager platform, Renesas was able to reach 100% combined coverage, allowing them to completely reach verification signoff. Using Cadence’s tools to revitalize their old verification environment was a resounding success, and greatly helped Renesas make the most of their existing work—and we’re looking forward to further endeavors with them in the future.![]()
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do I have to write full path for my simulation model?
Hello, we usually enter full path of simulation model (e.g. /A/B/C/my_model.lib.scs) before start simulation. I'm wandering: is there anyway to set a default path (e.g. /A/B/C) to spectre? Then I just enter "my_model.lib.scs" before start simulation and simulator will find model file under /A/B/C automatically. the advantage of such a thing is: when i porting design from process X to process Y, i don't have to update model path (assuming exacting the same model name) for my saved state. Thanks a lot.![]()
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Find shapes overlapped with a specific triangle shapes.
Hi, I would like to find any shapes that overlapped with a specific triangle shape. I know there is function call dbGetOverlaps to find all the shapes that overlapped in a searching bbox. But this function only able to find overlapping shape in a rectangle region. May i know is there any functions or algorithm able to find shapes overlapped with a triangle region. Thanks, KS.![]()
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RE: back to back square wave generation
Hello, Thank you very much. its working![]()
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RE: Find shapes overlapped with a specific triangle shapes.
A similar question was asked a few weeks ago. See my answer to this post: https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/40847/select-all-labels-inside-a-non-rectangular-shape-through-hierarchy Regards, Andrew![]()
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RE: back to back square wave generation
Since the amplitude seems to reduce a lot, you should also check which method is being used. This will be listed at the top of the tran analysis in the simulator log - check if it’s set to gear2ony. If you’ve set errpreset to conservative or explicitly set method to gear2only, I would suggest setting method (on the Options form on the tran analysis in ADE) to traponly. Gear methods (whilst generally a good choice for accuracy) are not so good for oscillators because they introduce a small amount of numerical damping which can cause oscillation to die out or reduce in some cases. Trapezoidal integration method doesn’t have this issue. Regards, Andrew![]()
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COMPONENTS OVERLAP DRC
Hi expert, There is special case that I have to overlap two components to reserve two kind of footprint. I can understand the overlap DRC error on this case. But there are still two other DRC type I do not know how to deal with. One is rats: It seems just can be route/connect to one symbols pin while another one is can not accesible. So the rats exsit. Am i should route all the two pins in different components? It seems i can not do it. How should I deal with this DRC error? Another one is: Drill hole to line same net spcaing(because the footprint is dirllhole) I guess this error is caused by the line and another pin which I do not connect.(I try to delete one symbols footprint and this DRC disappear) How can i deal with this kind of error. I think there are some cases that you have to reserve two footprint. Please teach me some about it. Thanks![]()
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RE: COMPONENTS OVERLAP DRC
My suggestion is to make 1 footprint which does not have any padstacks, so basically a mechanical footprint. Then you can overlay these 2 footprints without any pin/connection issues. In one case I had to place 2 TH transformers 90deg. rotated on top of eachother and only 1 pin was matching in location. So In 1 component I added 'unfix pins' property to this pin, changed the padstack to a SMT testpad and moved it away from the pin which was already there (from the 2nd component). Kr, Bram![]()
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Keyboard shortcut for running simulation
I use the following command as: hiRegisterBindKeyPrefix("Schematics") hiSetBindKey("Schematics" " F1" "sevNetlistAndRun(sevSession(hiGetCurrentWindow()))") My idea is similar as bindkeys for ADEL. But not work. Can you correct my idea. Regards![]()
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