That'd be great Steve. Here's the zip I had downloaded from TI: community.cadence.com/.../2018_2D00_12_2D00_18_5F00_14_2D00_22_2D00_36.zip![]()
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RE: 17.2 Padstack Editor -- Opening scripts for 16.6 in 17.2?
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RE: 17.2 Padstack Editor -- Opening scripts for 16.6 in 17.2?
Here you go community.cadence.com/.../data.zip![]()
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How to install old versions?
I'd like to install 17.2 S047. How do I do it? When I go to the download page all I see is the 17.2 base release and the hotfix to bring that to 049.![]()
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Verification Reflections on 2018
In my predictions for 2018 I had identified five key trends driving verification in 2018 – Security, Safety, Application Specificity, Processor Ecosystems and System Design Enablement, all centered around ecosystems. Looking back now as the year draws to a close, the key verification highlights that happened in 2018 indeed fit into these 5 categories, but there are also some surprises. Image source: BigStockPhoto First, on security and safety, this year indeed saw significant progress. Functional safety has become a huge topic especially in automotive but extends into other areas like medical and aero/defense application domains very fast. Cadence showcased usage by ROHM in a press release and at CDNLive Japan, as well as our work with ARM is this domain throughout 2018. Verification planning – a topic that we have been pushing for years with our Metric Driven Verification approaches - has started to extend in 2018 into three different areas: Classic “functional verification planning” is joined by “safety verification planning” with all the aspects around FMEDA (Failure modes, effects, and diagnostic analysis), and next up is “security verification planning”. Following Arm’s Simon Segar’s call to action at Arm TechCon 2017 to “put hackers out of business”, we saw a flurry of activities around Arm’s PSA (Platform Security Architecture) and Cadence showcased how we partner with companies like Tortuga Logic to connect with our Verification Suite at CDNLive and DAC. The key aspect to remember here, likely a key trend going forward, are threat models at several levels of abstraction – from RTL to system and software level – representing as early as possible the path that hackers could use to attack chip and system security, allowing verification to check proper counter measures. Also, Application Specificity has as I had predicted continued to drive very domain specific verification requirements. The 5G/Networking space drives very unique verification aspects. Getting 10Gbps data-rates, a million devices per square kilometer and 1ms latency to work out together is far from trivial. The trends in 2018 show that likely the high data rates will be the first focus (jay Netflix!) but the 5G verification challenges , especially for architecture analysis, remain tough and require extensive tool support for the right protocols. And short of improving the speed of light, the only way to achieve 1ms latencies seems to be to achieve data locality. In that context, “Edge Computing” may well be 2018 th tech term of the year and has spawned a flurry of design activities. The intensity with which activities have spawned in this domain, for instance at ArmTechCon, certainly surprised me. In the aero/defense space, DARPA has started the ERI program and spawned a lot of research activities , including Cadence activities in the area of AI/ML for EDA. Verification of Systems of Systems is a big topic, with emulation square and center as shown in presentations from AFRL and Cadence at GOMAC 2018, and emulation requirements were a big topic at the DARPA ERI forum. The area of AI/ML feels to me like the area of graphics development back in the mid 90’s, only bigger. Lots of start-up funding worldwide, especially in China, has further made hardware assisted verification – emulation and prototyping – a key necessity for these complex designs. Having an emulator that deals well with large capacity designs, offers flexible and efficient debug and optimized throughput puts us in a good spot here. Like IoT, this area overlaps other application domains quite a bit – like ADAS in automotive, as well as applications in medical, networking and others. The Server space saw further movements with Arm servers making significant inroads. It changes the datacenter aspects quite a bit with specialized workloads, and we at Cadence have announced availability of our tools on Arm based servers too . Eco-systems play a key role here as Arm announced the Server Ready program as an eco-system effort , for which for instance portable stimulus and emulation are used extensively as we announced at Arm Techcon . Expect more interesting news here in the years to come. Not an application in itself, spanning across application domains, IoT continued to be a key buzz word for the industry in 2018. Mixed signal verification is key for these relatively small designs (if they are edge nodes), and Cloud plays a key role here. For small designs users don’t want to have to build up all the EDA infrastructure in-house, so cloud activities like the one we have with Arm as part of the Design Start Program play here. But Cloud becomes important for big server class designs too - as announced in the Cadence Q2’18 earnings call that “Ampere Computing chose Palladium Z1 for the development of their next-generation ARM-based server chip. Palladium Z1 was chosen for its scalability for the large designs, state of the art debugging features, stability and availability over the cloud. Clouds everywhere, as also announced at DAC ! Processor Ecosystems did prove very important, perhaps even a bit more prominent as I had thought. My colleague Paul McLellan has covered this area nicely, most recently here . As stated in Paul’s blog, Qualcomm now also disclosed that it will be shipping RISC-V in a high-volume product in 2019. With others like Western Digital and NVIDIA already on the RISC V train, joint by several commercial IP Providers driving, the area of processor ecosystems has been most interesting to watch. Alliances are developing fast and friends on one day may be foes on the next, as I described here regarding the announcements at Arm TechCon . Last but most certainly not least, System Design Enablement has made huge strides in 2018, as could be seen at the Design Automation Conference in June. New alliances and ecosystems are forming in this area. Mathworks and National Instruments come to mind as key partners, helping verification and EDA extending into that domain. And of course virtualization has grown to be key to verification, both in augmenting physical interfaces for hardware engines, as well as adding higher levels of abstraction with virtual platforms, allowing the industry to enable “shift left” for earlier hardware/software integration. All in all, it turns out that my biggest mis-prediction from last year was that HBO’s ‘Game of Thrones’ would come to a conclusion in 2018. Not sure what I was thinking. The intensity around AI/ML chips was bigger in 2018 than I expected, and Edge Computing has pushed much more intensively than I would have thought. But the rest of my predictions was pretty much right on.![]()
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Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?
Spectre Tech Tips is a blog series aimed at exploring the capabilities and potential of Spectre®. In addition to providing insight into the useful features and enhancements in Spectre, this series broadcasts the voice of different bloggers and experts, who would share their knowledge and experience on all things related to Spectre. Enter your email address in the Subscriptions box and click SUBSCRIBE NOW to receive notifications about our latest Spectre Tech Tips posts. How to Perform EMIR Analysis in ADE Using Spectre APS? is the first blog in this series that takes you through the steps required to perform EMIR analysis in ADE using Spectre® APS. Happy Reading! As an analog or mixed-signal designer, you would be using Spectre APS in the Virtuoso® Analog Design Environment (ADE) for block-level designs. Lately, you might have seen a need for analysing IR drop and EM currents, and you wonder which Cadence tool to use for analyzing potential EMIR problems in your design. Well, you can use Spectre APS to do just that. Spectre APS provides a powerful transistor-level EMIR solution that uses a patented technology and enables you to perform EMIR analysis with high accuracy. The common simulation flow in circuit design requires you to first perform transient simulations on your pre-layout design. Once the layout is available, postlayout simulations are performed to check the impact of layout implementation. EMIR analysis is just another step in this transient simulation flow. It reuses the Spectre APS and ADE setup, and requires only a few minor additions for defining and enabling EMIR analysis. Setting up EMIR Analysis Options in ADE The Cadence EMIR solution is called Voltus-Fi XL , which uses Spectre EMIR as the simulation engine. While Spectre performs the circuit simulation, calculates the IR drop and EM current values, and stores them in a binary database, Voltus-Fi XL evaluates the EM-related techfile information, compares the calculated currents with the current limits in the techfile, and visualizes the EMIR results in the layout editor. The EMIR analysis options can be specified in the Spectre EMIR/Voltus-Fi XL Analysis Setup form, which can be opened by clicking Setup - EM/IR Analysis in Virtuoso ADE Explorer. By default, Dynamic (transient) EMIR analysis is selected in the form. You can specify the options for EMIR analysis in the Analysis , Solver , and Options tabs, which build the content of the EMIR config file. This is displayed in the Summary Information section at the bottom of the form. The content is written to the emir.conf file, which is included in the Spectre command line with the +emir command-line option, as shown below. spectre +aps input.scs +emir=emir.conf The most common EMIR analysis approach is to perform IR drop analysis on power nets and EM current analysis on power and signal nets. Make sure to connect the power nets to a DC voltage source to enable power net detection, and for obtaining the proper voltage reference for IR drop calculation. To set up the power net IR drop analysis: Click the Select button next to the Net Name field in the Analysis tab and select the power net terminals (VDD, VSS) on the DSPF subcircuit instance in the schematic. Select the max check box next to the IR Drop Analysis field. Click Add/Modify. The analysis statement is added in the Summary Information section. For EM analysis setup, repeat the above steps, select the DSPF subcircuit instance instead of its terminals, and select the avg and rms options next to the EM Current Analysis field. The related statement is added in the Summary Information section, when you click Add/Modify . Selecting a Solver The Spectre EMIR solution provides two methods for analyzing EMIR. The first method is the direct (default) method which provides SPICE-like accuracy by solving the entire circuit, including parasitics in Spectre APS. The second method is the iterated method that couples a linear solver for the parasitics with Spectre APS for circuit simulation. The iterated method provides higher capacity/performance with minimal accuracy loss ( .dspf.chklog file. All reported errors must be fixed; otherwise, you may spend hours in EMIR simulation just producing garbage. The spfchecker utility may also add a few additional options in the Summary Information section. These options are recommended for better mapping between DSPF and schematic netlist. To include the DSPF file in the simulation: Click Setup – Simulation Files in the ADE Explorer window. In the Parasitic Files (DSPF) section, click Click here to add a file and browse to the location where the file is located to add the file. In the netlist, the file is included with a dspf_include statement. Technology File Setup If the technology file (most common format: ICT) is provided by the foundry and includes the current limits for the EM current analysis, you can include this file in EMIR simulation. If enabled, in addition to reporting the IR drop voltage and the EM current values, it compares the EM currents with the current limits per layer segment, and reports errors where the limit is exceeded. To include a technology file in the simulation: Click the Analysis tab in the Spectre EMIR/Voltus-Fi XL Analysis Setup form. Add the file in the EM Tech File field located in the EM Rule Check section. EMIR Analysis Reports Once the DSPF file and EMIR configuration are set up, run the simulation in ADE Explorer. In addition to the regular ADE output, like voltage or current waveforms, EMIR simulation provides the following additional EMIR text reports: DSPF subckt pin current summary ( *.rpt_pin ) For each pin, maximum, average, and RMS current are reported. Power net IR drop report ( *.rpt_ir ) For each power net tap node, the IR drop voltage value is reported. The reference voltage is the voltage of the connected voltage source. Power and signal net EM current report ( *.rpt_em ) For each net resistor segment, the average and RMS current are reported. If a technology file is provided, the current is compared with the given current limit for the layer segment, and a pass/fail result with percentage is reported. These reports can be accessed by clicking Results - EM/IR Data - Report in Virtuoso ADE Explorer. Alternatively, the IR drop and EM current information can be graphically displayed using Voltus-Fi XL in the layout environment. The layout view can be accessed by clicking Results - EM/IR Data - Layout Analysis . For more information, refer to Voltus-Fi Custom Power Integrity Solution XL User Guide . Related Resources This blog introduces you to EMIR analysis and focusses on the basic Spectre EMIR flow using the ADE environment. The Voltus-Fi XL/Spectre EMIR flow provides many advanced features, such as static EMIR, Static Power Grid Solver (SPGS) point-to-point resistance checking, power gate handling, signal net IR drop, differential IR drop, what-if analysis, and self-heating analysis. In addition, Spectre EMIR analysis provides powerful options for optimizing EMIR accuracy and performance. For more details on the advanced features or accuracy/performance optimization, refer to the following: Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide IC6.1.7: Voltus-Fi EMIR Analysis Workshop- The DSPF flow (RAK) Spectre EMIR workshop in the Spectre installation (.../tools.lnx86/spectre/examples/EMIR_workshop) For more information on Cadence products and services, visit www.cadence.com .![]()
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RE: variable sweep in ADEXL
Well, you can't define the variables as you've defined them - I think that's unlikely that we'd support that complexity of setup in the future either because it would get horribly complicated pretty quickly. However, if you use ADE Assembler (rather than ADE XL), there's a feature called "Run Plans" which allow you to define a sequence of runs to perform, and importantly there's the capability to specify a "preRun" script which runs before the runs start. So for example: The simplePreRun.il script I've used is this: mode=maeGetVar("mode") printf("MODE IS %L\n" mode) case(mode ("1" maeSetVar("rval" "1k") maeSetVar("cval" "1p") ) ("2" maeSetVar("rval" "1k:200:3k") maeSetVar("cval" "1p") ) ("3" maeSetVar("rval" "1k") maeSetVar("cval" "1p:0.5p:5p") ) ) This checks the value of "mode" and adjusts the sweeps accordingly. There are different numbers of sweeps in each mode, for example. This isn't attempting to handle the situation where mode was swept, but hopefully you get the idea. It's a simple piece of SKILL code that uses the simple Maestro mae functions to get and set variables (you can set either global variables, or test variables - I kept it simple here and only adjusted global variables). Regards, Andrew.![]()
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Virtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available
The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download at Cadence Downloads . IC6.1.7 ISR23 ICADV12.3 ISR23 For information on supported platforms, compatibility with other Cadence tools, and details of issues resolved in each release, see: IC6.1.7 ISR23 README ICADV12.3 ISR23 README The links above are functional at the time of publishing. If you encounter any links that are now obsolete, visit https://downloads.cadence.com and select the release name you are interested in to access the related files. Here is a listing of some of the important updates made to IC6.1.7 ISR and ICADV12.3 ISR over the last few releases: Faster Netlist Generation for Analog Components in a Mixed-Signal Design (from ISR22) Use the new Create spectre subckt for extracted view check box to generate an optimized netlist for analog components in a mixed-signal design. Not only does the new option improve the netlisting performance but it also skips the mixed-signal elaboration step for these cellviews, saving the overall simulator processing time. Default Application to Open a Saved ADE State (from ISR21) Specify the default application where you want to open a saved ADE state. Use these while migrating to ADE Explorer or ADE Assembler. Wildcard Syntax for Saving PCells in Netlist (from ISR21) Use wildcards to specify PCell operating point parameters on the Save Options form. For more details on these and all the other new and enhanced features introduced in this release, see: IC6.1.7 What's New ICADV12.3 What's New Contact Us Please send questions and feedback to virtuoso_rm@cadence.com . To receive Virtuoso release announcements like this one, and other Virtuoso-related information, directly in your mailbox, type your email ID in the Subscriptions field at the top of the page and click SUBSCRIBE NOW. Virtuoso Release Team![]()
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RE: 17.2 Padstack Editor -- Opening scripts for 16.6 in 17.2?
Thanks a lot Steve. This works and I can see the symbols and pads. Appreciated. But now, the _brd script itself is having issues. It seems to go through correctly... It does a bunch of things, including what looks like re-drawing the symbols. But when all is said and done, the blank_Board.brd is unchanged, and that is the only board file in the directory. Any way you could run the script in 16.6 and include the updated .brd file here?![]()
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RE: Optimization of multiple tests in ADE-GXL
I just checked, and this isn't really possible. The closest is the "Feasibility Analysis" run mode which is specifically to run OpRegion checks first before moving onto more complex tests. However, if you had (say) a fast AC test and then a slower PSS or transient test, there's no way to tell it to try the fast test first and if that fails don't bother with the other. It's possible that conditional run mode might help, but I'm not sure it will really do what you want here. It's a good idea though... Regards, Andrew.![]()
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RE: Global optimization over several corners - question
Hi Aidan, The cost function is trying to minimise all of them with equal weighting, so that's probably going to have an effect along the lines of what you've observed. One possibility would be to add another measurement which has evalType of "corners" which is something like: peakToPeak(calcVal("FOM" "THETEST") ?overall t) and then specify that this should be < some acceptable limit (say <1 in or case). That would mean that another goal is to minimise the spread of across the corners (I suggested using a less than spec rather than minimise, because you may want it to work harder to minimise the FOM goal than just meet an acceptable spread). Regards, Andrew.![]()
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RE: Global optimization over several corners - question
Thanks, Andrew. I will have a go at that. All the best, Aidan.![]()
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getting class and subclass from ministatus
Hi I'm using a mini status window and is for the first time using the builtin class and subclass fields. But when I read the fields using axlFormGetField then I get a numeric value back. I've searched everywhere in the manual and looked over all axl commands with layer, class etc. to figure out how I can get from the numeric to the class/subclass which is what I'm looking for, Any hints is really appreciated, thanks. Best regards Ole![]()
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RE: displaying custom text in a schematic info balloon when hovering over an instance
Thanks for clarifying. Good to know it's already on an enhancement request list. The notion of adding a cdf parameter makes sense, but I don't think there is a direct way for e.g. users of a TSMC library of primitives to add cdf parameters to those components. Don't suppose you know any indirect ways ;-)...![]()
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RE: getting class and subclass from ministatus
Yes, I have had frustrations with this over the years. However, because the effect is to change the active layer, you can just use axlGetActiveLayer to see what values are set.![]()
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RE: getting class and subclass from ministatus
Hi Dave Thank you, I should have paid more attention to the deskription when mentioning active layer :-) /Ole![]()
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RE: Global optimization over several corners - question
Actually, Andrew, from your example, I see what to do - I really want to minimise the highest FOM over corners. So, I'm trying ymax(calcVal("FOM") ?overall t) - lower FOMs are better in my world - I think this will do what I want. I didn't know the evalType corners! Thanks, Aidan.![]()
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Problem with schMove()/dbMoveFig function
I am trying to rotate a schematic symbol in place. Or, put another way, I want to just change the orientation of the symbol and not change the location of the symbol. I have tried the functions below to achieve this but they all seem to translate the symbol to odd places: schMove( car(geGetSelSet()) schCV list( 0.0:0.0 "R90" ) ) schMove( car(geGetSelSet()) schCV list( car(geGetSelSet())->xy "R90" ) ) dbMoveFig( car(geGetSelSet()) schCV list( 0.0:0.0 "R90" ) ) dbMoveFig( car(geGetSelSet()) schCV list( car(geGetSelSet())->xy "R90" ) ) Alternatively I could probably just save the previous origin location and put it back after the move but I wanted to understand what I am missing here. Anyway, thanks for the help! (Bonus Points: I am trying to get this to work for something that would extract the underlying schematic from any given layout. So if you have any info that may help on this I'd appreciate it.)![]()
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RE: Windows 10 - anyone, anyone?
So it looks the latest Allegro physical viewer 17-2_v100318 has a problem where the arrow keys don't work for panning around the layout (on both Windows 10 and Windows 7). I had to revert back to 17-2_v041117 and arrow keys starting working fine again. Took me hours to figure out this stupid SW bug. Hope it helps someone!![]()
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RE: panning in Allegro v16.2
So it looks the latest Allegro physical viewer 17-2_v100318 has a problem where the arrow keys don't work for panning around the layout (on both Windows 10 and Windows 7). I had to revert back to 17-2_v041117 and arrow keys were working fine again. Took me hours to figure out this stupid SW bug. Hope it helps someone!![]()
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Measure power of opamp circuit
HI everyone, Can you help me? I want to measure power of inverting summing using opamp. however, i just use opamp model (written by verilog A) in adhlLib library. so, i dont know, whether i can measure power consumption. Thank.![]()
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