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RE: How to do UVM transaction recording with irun?
Please refer to: this article on controlling UVM transaction recording
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RE: How to simulate pnoise of fractional (non-integer) frequency divider
Yin, If using PSS, all frequencies must be an integer multiple of the fundamental because otherwise the result would not be periodic - you wouldn't be able to do the Fourier analysis of the interval if...
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RE: Display current view in window title bar
Hi Andrew, That solved it, thanks a bunch! I guess your hunch was right. I'll add that to my .cdsinit then. To answer your previous question, the window manager we're using is IceWM. Regards, Matthew
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RE: Display current view in window title bar
Thanks Matthew - IceWM isn't one I'm familiar with. I can only assume it has some problem with this character in window banners. Anyway, at least you have a solution for now! Regards, Andrew.
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IEDM 2017
The start of December means it is the International Electron Devices Meeting in San Francisco (it used to be in Washington alternate years but it is in San Francisco for the forseeable future). I have...
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RE: How to replace the Dummy net
First you need to create a net with axlDBCreateNet(), or fetch the dbid of an existing net with axlDBFindByName() Once you got a net dbid you can assign this to pins, vias or shapes with...
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RE: Length match diff pair from pin to via
Hi, If you are talking about length matching between the two nets in the diff pair from Via transition back to the Pin than it is available in Allegro 17.2 Static Phase Control at Via Transitions...
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RE: Cross Section Editor Impedance Calculator
Thanks, redwire. That cleared up some things for me. The paper steve referenced suggested "Trapezoid traces are specified by setting the trapezoidal_angle_in_degrees variable in the "Signal Analysis"...
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RE: Write Ocean-XL Script using Skill in IC 6.1.4
Matthias, No. I checked back and the request for this function was as a result of my CCR 820326 and was implemented in IC616 ISR3. How I described the need for it in the request was: Currently you can...
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RE: Code coverage for sv verification envrionment
You can enable with CCF command: select_coverage –b –class Options are available to selectively enable coverage inside certain classes. To De-select UVM package deselect_coverage -b -class -module...
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RE: calibreview fatal error
Hi, I can't seem to make a mentor community account. I am using my university email but it says Email Address Restrictions Please provide a company or university related email address to request a...
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Can I rebuild the pspice netlist from scratch?
I have a mixed-signal design with both simulated and non-simulated parts (marked with spsnetlist_ignore=true properties) . It was simulating fine, but at some point it stopped working - I would just...
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Can I rebuild the pspice netlist from scratch?
I have a mixed-signal design with both simulated and non-simulated parts (marked with spsnetlist_ignore=true properties) . It was simulating fine, but at some point it stopped working - I would just...
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RE: Can I rebuild the pspice netlist from scratch?
Ok... I wouldn't say I've "figured it out", but if anybody else ends up in this place the following steps worked for me (order is probably important): * Go through your entire schematic, starting from...
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RE: Length match diff pair from pin to via
Thanks, Steve. Do you know if it is possible to fix the T Point to a via? When the via is moved it doesn't seem to move the T Point.
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RE: Length match diff pair from pin to via
Hey Mike, what license has this option? I can't seem to find it using PCB Editor with the High-speed option.This is more along the lines of what I am looking. Do you know if it can be accomplished per...
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RE: Cross Section Editor Impedance Calculator
Hmmm...I left a detailed explanation a couple of hours ago but it seems to have disappeared. Maybe I'll write the explanation another day...
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RE: How to replace the Dummy net
Thanks Bruekers!! Actually, i have created the " test point footprint" and placed over the selected "cline seg " also need to assign the selected "cline seg net" into testpoint net. existing cline seg...
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RE: Cross Section Editor Impedance Calculator
That's happened to me... I would appreciate that explanation; brief would be fine...
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RE: What is default port order, and how to create it?
Anderew, thank you for the reply. Indeed the problems appear only when we used Verilog netlister of simulated with dspf files. But, I noticed that in last versions of Spectre it can properly take port...
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