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RE: ADEXL: Making Dependent Tests

Hi Andrew, How about if I want to use "result1" to define a variable for "test2" in the Corners Setup? Thanks

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2017: A Year in Breakfasts

So 2017 is over. Taylor Swift got into trouble for saying it was a great year and not being political enough. Well, I hope that I'm not going to get into trouble for saying 2017 was a great year for...

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vias alignment

Hi, I know it is not necessary to align vias but sometime I would like to do so. Is there a skill code to do so? Thanks, Regards, TiBo

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RE: Simulation with verilog-a model

I'm not that familiar with memristors (other than the odd article I've read on them) and so I didn't check to see whether the model you gave made sense. However, I can see that the idt is definitely...

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RE: Dynamically Changing the pulse width - vpulse/vsource

Vijay, Here's how I did it - I have a triangle wave at the clock rate, and then compare the signal with the triangle wave - and the Verilog-A is there just to generate the well-formed pulses at the...

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RE: how to process parametric sweep result in adexl

I'm not entirely sure what you mean by "detect the crossing point position of Vx". The crossing point with respect to what? I wondered whether you meant that if you plotted the graph of Vx at 5us...

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RE: Assura DRC doesn't zoom to errors

Jill, Did you press the left or right arrows as highlighted below? It's when you press these that it zooms to the error (because there could be multiple errors of each rule): Regards, Andrew.

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RE: ADEXL: Making Dependent Tests

I don't see what benefit having this as part of the corners set up would be. If you have the dependency in the variables, then you get the result from the corresponding corner anyway. Regards, Andrew.

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RE: How and where to find DRC highlight information.

Hi Andrew, Okay, Thanks for the information.

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RE: vias alignment

Align vias utility is there in APD/SIP License Route -> Resize/Respace ->Align Vias -Karthik.K

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code_coverage_Error_The_design_unit...

Hi All, I am doing code coverage, receiving following error; ncelab: 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc. TOOL: ncelab 14.10-s014: Started on Jan 09, 2018 at 12:09:19 IST...

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RE: Simulation with verilog-a model

Thank you for your answer Andrew. However, I think I did same with you but value of r1 does not vary in my simulation. also, this is my netlist....

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RE: ADEXL: Making Dependent Tests

You won't get the corners though, and it is a pain since ADE-XL sorts out the results differently when you sweep a variable instead of using the Corners Setup. I want to use "result1" and "result1a"...

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RE: code_coverage_Error_The_design_unit...

Hi Mahesh. This would appear to be a limitation of the coverage system, the extended help message explains a bit more detail as well as two possible solutions: linux> nchelp ncelab COVMDU nchelp:...

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Virtuoso System Design Platform Is Product of the Year

The title of this post says it all, but I'd better add a bit of color. Cadence was honored with an Electronic Products' Product of the Year award for the Virtuoso System Design Platform. This is the...

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RE: ADEXL: Making Dependent Tests

OK, so you're asking a different question from the one in the original post, and hadn't explained that what you were trying to do something different (this is precisely why the forum guidelines ask you...

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RE: Simulation with verilog-a model

It's because the magnitude of the integral part is tiny in your example because of the higher frequency of the sine wave. If you plot just I2:r1 (and not I2:R on the same graph) you'll still see the...

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RE: ADEXL: Making Dependent Tests

Thanks for your prompt response. What I am after is very similar to this thread; the only difference is the sweep/corner option. General forum guidelines often urge you to ensure, before you post a new...

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RE: ADEXL: Making Dependent Tests

I wasn't talking about general forum guidelines (presumably for other forums), but the specific forum guidelines for this forum (pinned post at the top of each forum). Anyway, if this worked before (I...

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RE: vias alignment

Thank for your help but I don't have the APD/SIP License. Regards, TiBo

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