Vijay, Here's how I did it - I have a triangle wave at the clock rate, and then compare the signal with the triangle wave - and the Verilog-A is there just to generate the well-formed pulses at the crossing points of the comparator - effectively the Verilog-A model is just a comparator, really. I'm showing a netlist and the model (the netlist is easier to grasp than a picture of the schematic where you can't see all the parameters). // I1 (pwmout 0 sig 0 triangle 0) PWM Vsig (sig 0) vsource type=sine freq=1k ampl=0.5 dc=1 Vtri (triangle 0) vsource type=pulse val0=0.2 val1=1.8 rise=0.5u \ fall=0.5u width=0 period=1u ahdl_include "forumpwm.va" tran tran stop=1m Here's the Verilog-A: `include "disciplines.vams" module PWM (outp,outn,sigp,sign,trip,trin); input sigp,sign,trip,trin; electrical sigp,sign,trip,trin; output outp,outn; electrical outp,outn; parameter real risefall=1n; parameter real low=0; parameter real high=1.0; real level; analog begin @(cross(V(sigp,sign)-V(trip,trin))); level=V(sigp,sign)>V(trip,trin)*(high-low)+low; V(outp,outn) <+ transition(level,0,risefall); end endmodule Regards, Andrew.![]()
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