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RE: Getting alt_symbols into existing design
I take my reply back - the reason I didn't see "Alternate symbol' in that pull-down menu was because that particular part did not have an alt_symbol defined. This works for the ones that do have the...
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RE: Creating Context File
Do you have to create your own .ilinit file? Where should the allegro.init file be? I read a different post that says to check where the ALLEGRO_ SITE variable but I don't know where that is... Would...
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save waveform to file during simulation
Hi, I'm trying to find a way to save waveform to a file while sim is running. I was able to find a few ocean scripts in this forum but I wonder if there's i.e.veriloga script that I can create a cell...
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probing signal in av_extracted_RC
Hello, I'm trying to probe some internal signal nodes of an RC extracted circuit, searching for root cause of a DC offset. The simulation is a simple dcOp from ADE-L on a test bench defined by...
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RE: Fourier Component in Cadence Virtuoso
Hi, I don't see there is RAK/workshop available for Fourier analogLib component. However, there is the following video and article that might be helpful, have a look. Using Spectre and the Fourier...
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verilog-a model help
Hi, I am new to verilogA. I am looking for veriloga code that generates a text output whenever gate of any transistor pmos or nmos rises to a file. Satendra
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Jitter measurement with PNoise Edge delay feature
Hello, I would like to characterize the impact of jitter on the pulse width (td) of the out signal shown below. I would like to understand how phase noise impacts/modulates the pulse width td, and...
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RE: Missing libraries when running Innovus Clock Tree Synthesis
Any resolution on this issue? I am seeing the same thing on Redhat 6 and innovus 17.12. Thanks, Ryan
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RE: Getting alt_symbols into existing design
Some elegant ways of accomplishing ALT_Symbol trade out in Allegro. This is great. Now to a caveat, if I use alt_symbols in capture how can you back annotate to capture to make the alt_symbol the...
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RE: probing signal in av_extracted_RC
Hi Hans Perhaps out-of-context probing is what you need: a. Create config view which uses the extracted view b. Simulate using schematic linked to config view c. From top level schematic, descend into...
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RE: Cannot overwrite default layout bindkey in ICADV
Hi Daron Perhaps it might be better to use the following SKILL script to toggle between orthogonal/anyAngle modes: procedure( CCStoggleSnapModes() let( (win) win=hiGetCurrentWindow() if(...
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RE: probing signal in av_extracted_RC
Hi Quek, Thank you for the suggestion. What do you mean exactly with step b) ? I'm simulating a config view with the RC extracted circuit I want to probe, I don't see how I can replace that with...
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RE: Behavioral simulation of standard cells: How? (AMS and other attempts fail)
Hi itos and somebody who found this post with the same problem I just would like to add one more solution here. In ADE, Setup --> Connect rules/IE Setup --> Check Connect Rule/Connect Module...
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RE: probing signal in av_extracted_RC
Hi Hans For step "b", I meant doing the simulation using a config view. I should written "extracted view linked to config view". You are trying to probe the voltage/current of the parasitic resistors....
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Is Ethernet Ready for the Automotive Market?
Consumer demand for advanced driver assistance and infotainment features are on the rise, opening up a new market for advanced Automotive systems. Automotive Ethernet allows to support more complex...
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Schematics cannot be mapped simulators
Greetings, I am using cadence 6.1.6. I automatically generate the netlist through a python code and run it from a skill script. I initially designed the circuit using the schematic editor and created...
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RE: Import from Synopsys IC Compiler to Virtuoso
Thanks Andrew for the tips. But is there a step by step manual or documentations on doing this? I am very new on using ICC & Cadence Virtuoso
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RE: Import from Synopsys IC Compiler to Virtuoso
Hi MoMiner1870, have you successfully done this? Do you have any step by step documentations on how to do it? I am very new in chip integration and step by step documentations are very helpful. Thanks
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RE: Creating a output of every DRC used on a design in Allegro 16.6.
This is certainly relatively easy to achieve with Skill.
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RE: Creating Context File
The allegro.ilinit file resides in your Skill path. Type "set" on the Allegro command line to get the settings of all your variables. Find allegro_site. The skill folder is a subdirectory of that...
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