Clik here to view.
RE: NC-Verilog user manual
All Cadence's product manuals are available online at http://support.cadence.com/ . If you haven't already registered there, simply use your corporate email address to register. You might need your...
View ArticleClik here to view.
RE: Changing the number of input bits in a DAC and problem in ADE simulation
Thanks, Andrew. It worked!! For some of those who are reading the forum, another step. After adding the symbol to the schematic, to connect the bus, see the schematic snip given below.
View ArticleClik here to view.
RE: Help with exporting .ART with SKILL
Thanks so much, this is what i wasnt able to grasp about rexEx. I was trying to use rexCompile, rexExecute, rexMatchp. Totally overlooked rexMatchList.. Now, how can i run axlRunBatchDBProgram through...
View ArticleClik here to view.
RE: Help with exporting .ART with SKILL
I played around and found 1 option that finally worked for me films = axlGetParam("artwork")->groupMembers filmLayers = rexMatchList("^[0-9][0-9][0-9][0-9][0-9]-[0-9]_[A-Z][0-9][0-9]$", films)...
View ArticleClik here to view.
RE: Assura LVS for Standard Cell Library with only Abstract View
Hi Quek, cna you describe this a bit further? I have an issue in bicmos8xp. I want to run LVS on custom inductor layout as blackbox but M1 ground layer keeps causing similar issue by generating...
View ArticleClik here to view.
RE: ade explorer set instance value
Well, one way to do this is to have a port (or vsource or isource if that's appropriate - you don't have to use "port" for RF simulations), and set it to sine all the time. Then specify the frequency...
View ArticleClik here to view.
RE: Assura LVS for Standard Cell Library with only Abstract View
hi Daihyun Would you please try adding ?blackBoxCell avParameter cmd to see if it helps? By the way, this thread has already ended more than 4 years ago. It would be best if you can start a new thread...
View ArticleClik here to view.
RE: Difference between V(P1,T1)
thank you for your explanation. I am trying to simulate a switch and when I used these statements in an 'if block', I get 'zero diagonal and jacobian' errors. Could you please suggest the best choice...
View ArticleClik here to view.
how to generate spectre netlist for all the schematics in 1 lib ?
Hi , I would like to generate spectre netlists for all of the schematic cell in my lib. What can I do ? I search in the forum but didn't the answer yet thanks Nhumai
View ArticleClik here to view.
RE: Difference between V(P1,T1)
If you want an explanation as to why your model misbehaves, it's generally best to actually show your model. My extra-sensory-veriloga-perception isn't working too well at the moment (I blame jet lag),...
View ArticleClik here to view.
RE: how to generate spectre netlist for all the schematics in 1 lib ?
Hi Nhumai, Something like the following (untested) code: simulator('spectre) lib=ddGetObj("libName") foreach(cell lib~>cells when(ddGetObj(lib~>name cell~>name "schematic") design(lib~>name...
View ArticleClik here to view.
PCB Editor: possible to adjust embedded net names "density"?
Hello! I'd like to increase the "density" of the net names in PCB Editor, as sometimes (specially in close zoomed-in views) large shape areas don't display a label, and one needs to "zoom-out" to catch...
View ArticleClik here to view.
RE: how to generate spectre netlist for all the schematics in 1 lib ?
Hi Andrew, I am new to skill script please help to let me know how to use it ? thanks Nhumai
View ArticleClik here to view.
RE: how to generate spectre netlist for all the schematics in 1 lib ?
Hi Nhumai, Either take the code above (with the correct library name where it has "libName") and paste it in the Command Interpreter Window (CIW), or probably better to put in a file, save the file,...
View ArticleClik here to view.
RE: Unable to import psm path
You can use wildcards in dbdoctor so try browsing for a padstack (filename.pad) then edit it to say \*.pad which will do this as a batch on all padstacks. Repeat for *.dra. That should seed things up.
View ArticleClik here to view.
RE: NC-Verilog user manual
Hi Stephen, I registered for the support, thank you for this information. Also the trick with the "decompile " in ncsim, worked like a charm. I used the following command: ncdc -output ./mydc.v...
View ArticleClik here to view.
RE: Replace "`includes" with in-line modules - NC-Verilog
I managed to found the solution. In ncsim environment, after the compilation of the top Verilog netlist, I run the command ncdc -output ./mydc.v my_lib.top:snap and it generated a top Verilog file with...
View ArticleClik here to view.
Clik here to view.
RE: Difference between V(P1,T1)
If you want to learn how to best model a switch (and why), I would suggest you to take a look at chapter 3 of the Mixed-Signal Methodology Guide, which is available at...
View ArticleClik here to view.
Turning Fixed Costs into Variable Costs: Foundries and Clouds
One trend that has been accelerating for a couple of decades is turning fixed costs into variable costs. Often this is what is behind outsourcing some capability. Sometimes it is driven purely by lower...
View Article