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RE: Bottom soldermask Gerber Problem
I guess I didn't describe the board properly. I have a plane on the bottom side and some tented vias, but no features in the bottom soldermask. I attached the file that is generated. My gerber viewer...
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Opening ModGen (Module Generator) in Cadence
I was working with ModGen two weeks ago and it was fine. Now, I wanted to go back and do some modifications but I cannot open the menu! I used the following path: Windows -> Assistant ->...
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RE: Bottom soldermask Gerber Problem
Inside your Gerber file you are missing XY coordinates and a few other things. Compare it to an artwork file that works. You will see what I see. I did try to re-import your file back into the PCB...
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Running parallel processes in SKILL code
Hi, I am writing an oceanXL script to launch multiple runs in parallel. While I set each run with ocnxlRun( ?waitUntilDone nil) in the loop to set up the circuit, after all runs are defined and...
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RE: Opening ModGen (Module Generator) in Cadence
The constraint manager is only in Virtuoso Layout Suite XL (or GXL). You're using VLS L from the picture, and so the assistant won't show up. ModGens themselves require GXL licensing and so must be...
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RE: Virtuoso, monte carlo simulation to measure fervency of ring oscillator
Hi Amin, I assume you mean a Physically Unclonable Function (unless Uncolnable is some term I've never heard of) - not that this is terribly relevant to the question. I still don't understand why you...
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RE: Vref Opamp Simulation
Your first step would be to ask a question that makes sense. I have no idea what you're asking (or why you're asking it in the SKILL forum). Kindest Regards, Andrew.
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RE: Opening ModGen (Module Generator) in Cadence
Thank you Andrew. Using the Layout GXL, the problem is solved and I am able to work with ModGen. Thanks again!
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RE: addStripe command for multiple power domains
try getting rid of the start/stop arguments.
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RE: Hierarchical Design using characterized blocks timing issues
Did you balance the clock tree to your blocks? I haven't done clock trees in a long time, but in the old CTS method, we would use a "macromodel" that basically told the top-level what the insertion...
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RE: Dangling wires/extra net length using -sroute command
this seems strange - are the vertical stripes on grid?
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RE: Encounter's "common timing library"
what version are you using? the libraries should be set up using a MMMC file so that you can have as many analysis views as your design requires...
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Abstract tool shows this warning
I am trying to generate .LEF file of a custom design inverter using Abstract tool.I used M2 M3 metal layers in this but when I passed this design it shows this WARNING (ABS-245): Failed to perform the...
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RE: Dangling wires/extra net length using -sroute command
It's fixed....I had to decrease using the modifyPowerDomanAttr the length by about 0.12 um....so instead of say, 30 it fixed to 29.844 say... Thanks!!
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RE: addStripe command for multiple power domains
precisely...using both x and y components doesn't exactly help...use either of them....also using -minGaps {...} is better instead of -gapEdges
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RE: Encounter's "common timing library"
yes..this happens as your MMMC file overwrites it...so set up individual views for each instant...something like _MAX_TYP $LIB_PATH and if you have set_analysis_view enabled or update_delay_corner make...
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RE: Constraint region overrides net based constraints
The priority is fixed and documented in the Constraint Manager user Guide. In 17.2 use the Cadence Help and search the PCB Editor documentation for "override" it will be the first "hit", or get the...
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RE: How to set Vref of Opamp in adhLib
Hi, You should read the verilogA of the block to see how it is modeled and how to make it works.
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RE: How to set Vref of Opamp in adhLib
Yes. Thank. I simulated it on Spice, and I see it works. So I think it maynot work on Cadence.
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