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RE: Hierarchical Design using characterized blocks timing issues

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Did you balance the clock tree to your blocks? I haven't done clock trees in a long time, but in the old CTS method, we would use a "macromodel" that basically told the top-level what the insertion delay inside the block was, so that the top-level tree could balance the leaf flops. Even with that though, you are likely to see some timing violations in flat timing that you did not see at the block-level. This is normal.

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