On the technology I am using the default via width for the top metal is not DRC clean for our application. I figured I could make a via variant to solve this. The issue is that once a variant is made, its rows and columns are fixed e.g. if I make a variant and leave the rows and columns at 1x1, every array I make using the variant will be fixed at a size of 1x1. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/34388/problem-with-auto-via-using-custom-via-variant This was asked two years ago but there was no real solution given. Any ideas?![]()
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