hi Andrew, one more thing regarding "reg" in VerilogAMS. I create VerilogAMS view from IC617, using the exact example as from AMS LRM, but the Text Editor still complains " `reg' is not a reserved keyword now but will be one in a future release." when I click "Check and Save". reg [8*12:1] stringvar ; initial begin stringvar = "Hello world!" ; end you sure "reg" is supported in VerilogAMS? I just like the way for easy string bit(s) access. thanks, David![]()
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