RE: possible to instantiate Verilog module in VerilogA?

hi Andrew, sounds like a good trick. And I am able to make the "config" happy which finds the verilog cell (say child) as instantiated inside VerilogAMS block(say parent cell). but when compiling, it still complains this child Verilog cell is referenced but not defined yet. Error found by spectre in `parent', during circuit read-in. ERROR (SFE-23): "...parernt/verilogams/veriloga.va" 246: The instance `child' is referencing an undefined model or subcircuit, `child'. Either include the file containing the definition of `child', or define `child' before running the simulation. some clue to make it work? thanks a lot, David