Given that I'm not realistically going to study a 60-odd page thesis to answer a question on the forums (you have to do something for your degree!) I merely quickly scanned it. The system is a sub-Nyquist undersampling system - but it's using a PRBS source, not a sinusoidal input. A sinusoidal signal which is coperiodic with the clock is going to be sampled with the same value at each clock edge, so you're going to get a constant output. In your case though, the first problem is that you haven't set the parameters of the ADC. If you have the signals as you've described, then you should (on the edit properties form for the ADC) enter (first pick the CDF filter to be veriloga so that it shows the parameters), then fill in the vmax, vmin (to control the maximum range of your input signal so that the ADC uses the full range), and vth to be the mid-point of your logic signals (so 0.5V here). I also set "one" to be 1 so that the digital outputs of the ADC have the same voltage range as your clock: That will at least make sure that the ADC is clocked (it won't be otherwise) and that the range of the signals that the ADC is converting matches your input signal. The next problem is that your input signal is co-periodic with the clock. To illustrate this, I've plotted the clock signal you describe together with the 4GHz sine wave, and put vertical markers at the 0.5V rising crossing points of the clock: As you can see, the sample points are identical so the ADC would convert the 3.14mV for each sample - it will be constant. Hardly surprising given they're co-periodic. Presumably (without reading the thesis), the input signal is not periodic (if it's a PRBS), and so you'd end up getting a varying output, which presumably is useful in this circuit. Just to explain what happens when you apply a frequency above Nyquist, I simulated with the same settings you did but with a 4.1GHz sine input. Here's what I get: Note that the frequency at the bottom (this is the re-constructed digital output of the ADC) has a sine wave at 100MHz - which is the "beat" frequency of the 4.1GHz input signal and the 800MHz clock. This is the aliasing effect you'd expect - but with a 4GHz input signal, you'll end up with a 0Hz (DC) "beat" frequency. I think in the situation in the thesis, the input signal is non-periodic, so you'd still get some output though. The picture on Page 40 of the thesis (which you posted above) is just (as I said) showing the result of a ramp over 50ns between vmin and vmax. It's not the result of a 4GHz sine wave input. Regards, Andrew.![]()
↧