When a change comes in from your IC design partner, it can be met with trepidation. How drastic is the change? What impact will it have on the package routing and (potentially) even the layer count needed to fan out the die? Will the bond finger tiers need to be redone to keep wires from crossing and raising the unit cost with the need for more extensive manual checking? The simple fact is that ECOs are a part of our daily job. There’s no avoiding them. Instead, embrace the changes as a part of your flow and you will find the flow that much easier. How can you do that, do you say? Read on, as we cover some of the considerations and the ideal solutions for bringing a change in from the mundane to the extreme. Die Replace First off, most ECOs coming into package substrates will affect the die components. The BGA or package interface is typically more under control of the package designers themselves. While it will change, those changes are driven by you, for your benefit, unless the PCB on which you will mount the finished package changes extensively. This is important! DO NOT delete/unplace the component you are trying to update! Why, you ask? Because if you do that, the system loses the knowledge of what the pin to escape routing was. This is key to getting the cleanest routing adjustments when you bring the ECO modifications in. Below, we can see the options that you’d find when processing an update through any of the die import mechanisms in Allegro® Package Designer Plus. For wire bond dies, the options are a little bit different (you’re processing 3D bond wire connections to fingers and other dies instead of vias and traces), but the mapping options to pins remain consistent. I think the most common option here would be to reconnect the etch by net name. If you swap the nets on two pins of the die, you will normally want those connections to swap, too. If you can, though, update by pin name or number, or even to the closest pin location to the escape routing terminus. This is ideal in scenarios where the BGA is fully in your control – the net assignment can be pushed out through the routing all the way to the BGA ball and plating bar pin. In these cases, it is possible to avoid any change to the package routing… of course, you’re pushing the problem out to the PCB designer. Routing Adjustments What happens to the routing based on pin movements? Look below, where I’ve shifted the pins as part of the ECO. Die replacement takes this and stretches the final segment of the traces to the new pin location. Vias, via stacks, and structures, and moved to the new pin origin. Instead, the first cline segment that connects to the end of the via or structure is stretched. This is important if those structures are key to proper escape routing. The structure remains unchanged, still perfectly aligned to the center of the pin. As part of a differential pair, both structures will offset the same way, maintaining proper alignment. While I’ve accentuated the changes above for clearer visibility, if the pin shift is subtle, the via might still overlap the pin, maintaining the signal connectivity. However, not being centered on the pin can lead to manufacturing or yield issues. It’s better as much as possible to keep things optimally aligned. Let the system manage this for you and you don’t need to concern yourself. One less thing off your personal to-do list (mine’s bigger than I can get done, so I will always take a freebie or two!) is not something to toss aside. Safety Nets In the event you forget some of the above (or are worried that things are misaligned due to some other step in your flow), the Cadence tools offer you a check – with the ability to auto fix – of via to pin alignments. Under the Tools menu, find the Package Design Integrity command. There, under the Manufacturing category, you’ll find the Via-Pin Alignment check (there are also via stack alignment, redundant padstacks, and many other checks that will preemptively catch issues). Use this check any time during your design process to set your mind at ease as to any potential problems waiting to happen. Closing Notes The concerns for different types of ECOs will vary. If you have a need for different behavior than offered today, please reach out to your customer service team. Explain your needs, and we will do everything we can to help you out with that. Should you need to add an integrity check like the ones mentioned earlier, you can add your own custom checks, too. Search for the axlPackageDesignCheck series of functions in the SKILL function documentation of your installation hierarchy. At the end of the day, the most important thing to remember is that you’re not in this alone. We’re here to help!![]()
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IC Packagers: Keep Fan-Out Routing Aligned During ECOs
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spectre fails to finish transient sims
Simulation abort with error and does not finish. Any suggestion on this ? Notice from spectre at time = 3.37543 ns during transient analysis `tran'. Newton iteration fails to converge at time = 3.37543 ns step = 1.50009e-21 s. Disaster recovery algorithm is enabled to search for a converged solution. Notice from spectre at time = 3.37677 ns during transient analysis `tran'. Newton iteration fails to converge at time = 3.37677 ns step = 1.50009e-21 s. Disaster recovery algorithm is enabled to search for a converged solution. Notice from spectre at time = 3.37821 ns during transient analysis `tran'. Newton iteration fails to converge at time = 3.37821 ns step = 1.50009e-21 s. Disaster recovery algorithm is enabled to search for a converged solution. Notice from spectre at time = 3.37977 ns during transient analysis `tran'. Newton iteration fails to converge at time = 3.37977 ns step = 1.50009e-21 s. Disaster recovery algorithm is enabled to search for a converged solution. Notice from spectre at time = 3.3815 ns during transient analysis `tran'. Newton iteration fails to converge at time = 3.3815 ns step = 1.50009e-21 s. Disaster recovery algorithm is enabled to search for a converged solution. Further occurrences of this notice will be suppressed. Error found by spectre at time = 3.5829 ns during transient analysis `tran'. ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified.![]()
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RE: Psat calculation w/ load
Hi Andrew and Shawn, Thanks for those helpful tips. I tried the PSS analysis and it is my first time I worked on it. In this schematic, I used two ports and the input port has fin, Pin as variables.The goal of mine is to plot Psat Vs frequency. So I tried the PSS and used direct plot to extract P1dB (output referred) at different fundamental frequencies and plotting them separately in excel. I have few questions over the analysis. Q1. Since the TIA is meant to use a current source at input, the usage of an input port (a voltage and series 50 ohm resistor) seems equivalent. But is this the right way? Q2. I have to try the conservative/moderate/liberal settings to have convergence met. I also changed the Pin range and number of harmonics. Despite of that, when the fin is at 10G, the simulation doesnot converge. Notices like "Zero diagonal found happens at the final sweeps although the initial ones run" , "Trapezoidal ringing", Why does this happen? Thanks, -Rakesh.![]()
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RE: AMS Simulation Error for INCISIV Version
Thank you for reply Andrew. You think I will have problems if I proceed with the old version? If I am going to use a new version INCISIV, how should I create/involve it in my set up?![]()
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RE: AMS Simulation Error for INCISIV Version
Well, using an old version is more likely to have flow bugs - software improves over the years. To use a new version, you need to ensure that /tools/bin or /tools/bin are in your UNIX path (if you type "which irun" or "which xrun" in UNIX you should then find the executable). How you control that, I can't say, as this will depend on your UNIX setup in your environment. Since you found a way of switching the IC version used, I'd expect you to have a similar way to switch the INCISIVE or XCELIUM versions (many organisations use "modules" to do this). Andrew.![]()
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RE: spectre fails to finish transient sims
You may want to contact customer support as debugging in the forum is quite hard. A good starting point would be to specify +diagnose on the Spectre command line (in recent IC versions there's a checkbox for this on the Setup->Environment form in ADE, or worst case you can type "+diagnose" in the User Command Line Option field on the same form). This will provide a lot more detailed diagnostics as to why the tilmestep is collapsing (it's probably some discontinuity or poor VerilogA model). Regards, Andrew.![]()
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RE: AMS Simulation Error for INCISIV Version
The newest version that I have in the UNIX path is INCISIV13.10. I don't know how or where should I provide a new version. please let me know if you have any suggestion.![]()
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RE: AMS Simulation Error for INCISIV Version
I don't know what you mean by "how or where should I provide a new version". If you mean were can you get a newer version from, well, software can be downloaded from our http://downloads.cadence.com site. I'm sure your organisation cannot be limited to 7 year old software versions (especially as IC617 is newer than that). Regards, Andrew.![]()
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BoardSurfers: Allegro In-Design Coupling Analysis: Crosstalk Mitigation without Models
Just as social distancing minimizes human contact to prevent the spread of disease, PCB spacing constraints minimize coupling between traces to prevent crosstalk problems for drivers and receivers. In cases where a safe distance cannot be maintained, wouldn’t it be nice to have a very quick, accurate test to provide additional peace of mind? The Allegro® In-Design Analysis Coupling Workflow provides a perfect method for testing the effectiveness of spacing constraints or the risk when these constraints can’t be met. The Coupling Workflow powered by the Sigrity hybrid solver makes it easy for anyone with Allegro to run analysis on all nets of a routed board without the need for external tools, lengthy simulations, or complex IBIS-AMI driver and receiver models from chip vendors. The results are based on the full cross-sectional geometry and include coupling from different layers of the board. Coupling coefficients can be overlaid directly on the PCB canvas making it easy to adjust routes to correct for coupling issues. The DDR signal bus shown here generally has coupling coefficients within an acceptable range with a few exceptions where traces are passing over a reference plane gap. The red segments on the canvas are easy to identify, and the dominant aggressor is listed for each segment in the results table or as a datatip on the canvas. By moving traces away from a reference gap, increasing their spacing, or making sure they don’t overlap on adjacent layers and then re-running the Coupling Workflow, designers can quickly ensure they are reducing trace coupling in their design. PCB designers can ensure their routes have minimal crosstalk without the need for a signal integrity expert or external tools. In addition to viewing results on the canvas, coupling coefficients can be sorted and filtered in a table with summary and detailed views. Results can easily be exported as a CSV file, making it possible to quickly create post-layout reports and share your design details outside of Allegro. Click here to watch a short demo of the Coupling workflow in action. You might be interested in the following links: Sigrity Aurora : Traditional signal and power integrity (SI/PI) analysis for pre-, in-design, and post-layout PCB designs. Allegro Right First-Time Design : Constraint-driven design with an integrated layout and analysis solution to help avoid making mistakes. Sigrity SPEED2000 : One tool to perform electrical rule checking, interconnect model extraction, signal integrity (SI) and power integrity (PI) studies, and design-stage electromagnetic interference analysis.![]()
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RE: Sub Menus are too large
Perhaps your windows was installed on a high-resolution screen. Window automatically selects a large font to compensate this. Check the following registry entries, If they are different then change then to the following values (= default font size) [HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows NT\CurrentVersion\Fonts] "MS Sans Serif 8,10,12,14,18,24"="SSERIFE.FON" "MS Serif 8,10,12,14,18,24"="SERIFE.FON" "Courier 10,12,15"="COURE.FON"![]()
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axlSaveDesign and axlRunBatchDBProgram
Hi All Since axlRunBatchDBProgram runs on a saved design then it can be necessary to save the board before running axlRunBatchDBProgram. However, reading the documentation for axlSaveDesign it has the following clause "Use axlRunBatchDBProgram, if the intent is to save the design to run another program." There are however no documentation on saving the design using axlRunBatchDBProgram So what is the solution here? Best regards Ole![]()
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Automotive Ethernet
Automotive networking is perhaps the latest application area for Ethernet. But Ethernet in some form has been going for nearly 50 years. Let's start with a little history. History Ethernet really started in 1971, although it was called AlohaNet. It was the first wireless packet data network. As you might guess from the name, it was created in Hawaii. The University of Hawaii had its main time-sharing computer system on the Oahu campus, but there were outposts of the University on other islands. It was satellite-based. I won't go into all the details, except for one. The system used a shared radio channel. When a system wanted to transmit, it would wait until the channel seemed to be free, and then it would transmit to the satellite. It would also listen to the satellite downlink. Due to delays, it was quite possible that the channel only seemed to be available when transmission was initiated, and that the packet would collide with another packet from another transmitter. The first level of retransmission was to notice that this had happened, wait a little, and then try again. There was a usual network protocol for handling end-to-end acknowledgment, packets that were damaged in other ways, and so on. When Robert Metcalfe and David Boggs at Xerox PARC designed the original Ethernet in the early 1970s, some of the design was based on AlohaNet, which Metcalfe had studied as part of his PhD. Despite the name, Ethernet didn't run in the ether like AlohaNet, it ran over coaxial cable. But it had some of the same features: transmit if the channel seems to be free, listen for collisions, retransmit automatically. All the Alto computers at PARC were networked with the 3Mb/s original Ethernet. The first commercial Ethernet was the 10Mb/s so-called DIX Ethernet, launched in 1980. DIX stood for DEC-Intel-Xerox, the three companies that created the standard: a company that built computers and needed a local-area-network technology, a semiconductor company that could build the chips to bring the cost down, and the original company that developed the idea (and was the only company with any experience running such a network). The "type" of networks went by the unwieldy initials CSMA/CD, for carrier-sense multiple-access collision detect. The 10Mb/s Ethernet also ran over a single shared coaxial cable. This soon became IEEE standard 802.3. Gradually all other network technologies, such as Apollo's token ring, the Cambridge Ring, and others, were superseded by Ethernet. The shared coaxial cable was replaced with point-to-point twisted pairs (standard telephone wiring) in the 1990s, with switches and routers to get traffic to its destination. Today, nearly 50 years later, Ethernet's triumph over other wired (or fiber) networking technologies is pretty much total. Cloud data centers connect their servers to the top-of-the-rack router with Ethernet, the top-of-the-rack routers are connected within the data center with Ethernet. Data centers are connected to each other with Ethernet. Automotive Networking But in automobiles there were other wired standards, notably CAN bus (which I'm always disappointed doesn't stand for car-area-network but for controller-area-network). CAN bus worked well when very little data was being moved around inside a vehicle: moving the seats, adjusting the mirror, tuning the radio, sonar for reversing. But the move towards ADAS (advanced driver assist systems) and autonomous driving has changed everything. Now the typical car architecture is to have a powerful central computer, and connect it up to feeds from video cameras, radar, and lidar. These require a lot of bandwidth, more than CAN bus (and other technologies like LIN or FlexRay) can provide. When you need a wired network with a lot of bandwidth, there is really only one choice since there is the opportunity to leverage the entire ecosystem of chips, software, test equipment, network monitoring, and more. Another advantage is that Ethernet runs over unshielded twisted pair. This means that it can significantly reduce the weight and complexity of the wiring harness. I have heard that these harnesses can reach 50Kg (100 lbs) which is a lot of weight affecting mileage, not to mention a lot of cost in manufacturing it. Since the car is literally assembled around the harness, if the harness fails, the car is usually scrapped — it is cheaper to buy a new car than attempt to replace it. Bob Metcalfe, the inventor at PARC of the 3Mb/s original Ethernet (and the Metcalfe of Metcalfe's Law) said in the foreword to Automotive Ethernet: The Definitive Guide : As I have been saying for 40 years: “If it’s networking you need, Ethernet is the answer; what is the question?” In this case, we might consider two related questions. “What took the automotive world so long? And how will it now use Ethernet going forward?” So cars are going to contain Automotive Ethernet. Automotive Ethernet The above diagram shows that architecture with devices spread around the car and linked back to the head unit and the switch by Automotive Ethernet. In addition to the Ethernet capabilities required in data centers, Automotive Ethernet also needs to support Time-Sensitive Networking (TSN) and the IEEE 1722 Audio-Video Bridging (AVB) Transport Protocol. These technologies allow the network to provide quality-of-service (QoS) guarantees on latency and synchronization. Doing an Automotive Ethernet Design There are three parts to an Ethernet interface, the PHY, the MAC, and the controller. Cadence has Design IP (DIP) available for all three parts. The PHY is the analog cell that actually connects the chip to the physical medium, in the case of automotive Ethernet, this is the twisted-pair copper, also known as 100Base-T1. The Cadence 10Gbps Multi-Protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising performance, power, or silicon die area. The PHY IP is a lower-active and low leakage power design crafted for mobile, wireless IoT, consumer, and automotive designs. The MAC is the media-access controller that handles all the other aspects of the interface beyond the PHY. Compliant with IEEE Standard 802.3, the Cadence IP for Gigabit Ethernet MAC is highly customizable with support for an integrated 1000BASE-X PCS, a high-performance DMA with advanced AXI offloading features and descriptor caching, QoS, 1588 and TSN/AVB features to support any application. It supports a host of other features including VLAN, TCP/IP offload, and remote network monitoring (RMON). The Cadence 10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications is a highly customizable soft controller IP, which is compliant with the IEEE 802.3 standard. To support a range of Ethernet applications, the Controller IP for Automotive features integrated 1000BASE-X and USXGMII PCS modules, a high-performance DMA with advanced AXI offloading capabilities and descriptor caching, QoS, and IEEE 1588. The Time-Sensitive Networking/Audio-Video Bridging (TSN/AVB) functionality enables unified Ethernet communication of critical data without traffic congestion in shared networks. Furthermore, the Controller IP for Automotive supports a host of other features including IEEE 802.3az Energy-Efficient Ethernet (EEE), VLAN, TCP/IP offload, and remote network monitoring (RMON). For analyzing the wires that make up the network, use Sigrity SystemSI Automotive Ethernet Channel Simulation. This lets you analyze the ECU-to-ECU communication performance via the physical Ethernet channel with Sigrity SystemSI technology for automated chip-to-chip signal integrity analysis. This lets you test different combinations of IP, different cable lengths, shielding vs non-shielding, aging, and compliance checks for automotive Ethernet 100Base-T1 PHY. For analyzing the transmitters and receivers, Automotive Ethernet Compliance Checks for 100Base-T1 BroadR-Reach PHY involve provided IBIS and AMI models for the IP. For a deeper dive into how this is done, see my post AMI and IBIS: Who Put the Eye in AMI? Using Sigrity SystemSI Simulation can characterize output droop, power spectral density, jitter, clock frequency, distortion, and return loss. Learn More Full details are on the Cadence Automotive Ethernet page . Datasheet for the Automotive Ethernet controller IP . Datasheet for the Gigabit Ethernet MAC IP . Datasheet for the 10G Multi-Protocol PHY . The product page for What's New in Sigrity . A white-paper Improve Reliability and Redundancy of Automotive Ethernet Through Open Standards . Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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BSIM4 import into AWR
Hello, I am trying to import a cadence BSIM 4.4 model file (.scs) into AWR from a foundry PDK (built for Spectre RF). The parsing and symbol creation go through fine but it comes up with a load of "Variable not valid" errors. Some examples below: "toxe_n33 - Equation Error: Variable 'dthkox@' is not valid" Same for: mc_gl_f@, cnr_toxd@, dthkox@, cnr_n33@, etc... I expect the Cadence environment takes care of these somehow. Wondered if anyone knows a solution for this or has come across this before. AWR version I am using is:13.02r build 8379 Rev1 (104876) (64-bit) Many Thanks, Chris.![]()
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BSIM4 import into AWR
Hello, I am trying to import a cadence BSIM 4.4 model file (.scs) into AWR from a foundry PDK (built for Spectre RF). The parsing and symbol creation go through fine but it comes up with a load of "Variable not valid" errors. Some examples below: "toxe_n33 - Equation Error: Variable 'dthkox@' is not valid" Same for: mc_gl_f@, cnr_toxd@, dthkox@, cnr_n33@, etc... I expect the Cadence environment takes care of these somehow. Wondered if anyone knows a solution for this or has come across this before. AWR version I am using is:13.02r build 8379 Rev1 (104876) (64-bit) Many Thanks, Chris.![]()
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RE: Harmonic Index of PSS data is not found?
THere could be more at play here as getting PSS/HB to behave for large autonomous circuits seems very iterative in terms of getting the correct settings, but indeed i couldn't get HB to converge even with just 150 harmonics for the same circuit for which shooting seems to. And while we are at it, I have some doubts about the validity of using Jc from Direct Plot form post pnoise to my application which has a specification of peak to peak period jitter = 10 ns (in a 10000 cycle window). As per the formula 1.18 in "Jitter Measurements using Spectre RF AN" also stated here https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000007MnBUUA0&pageName=ArticleContent , Jc (from the definitions in Cadence docs, Jc matches exactly the definition of period jitter in other literature) for my design comes out to be sqrt(2) or 3 dB lesser than what Jc from Direct plot spits out. I established this by exporting the phase noise data from my results in cadence spectre and using the said formula in MATLAB/ Excel on exported data. It seems that Jc in direct plot does not convolve the phase noise with the high pass function [sin(pi*f*k.Tc)]^^2 to calculate Jc making it effectively a measure of absolute jitter rather than period jitter ( Eqn. 3 and 8 here: D. C. Lee, "Analysis of jitter in phase-locked loops," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 11, pp. 704-711, Nov. 2002, doi: 10.1109/TCSII.2002.807265.) Would appreciate if some more light could be shed on this? Thanks, Sharjeel![]()
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RE: BSIM4 import into AWR
Hi Chris, It's possible to import spectre models into MWO by importing them as a spectre netlist. When you do so, you need to ensure that you are importing all of the model as most model files you find in a PDK will be referencing other files to get things like corner and/or mismatch info and all necessary parameters need to be clearly defined for it to simulate. To actually use the model in an MWO schematic you need to call it from a simple netlist of the format: simulator lang=spectre inline subckt devicename (D G S B) parameters w=5u l=0.25u M0 D G S B mymodelname w=w l=l ends devicename model mymodelname bsim4 +type = n +version = 4.4 +lmin = 2.5e-7 ... ... ... +noic = 1.4e-10 This will give you a device you can place on a schematic which is scalable for w & l. The spectre netlist parser in MWO is fairly basic so if there are special characters in the parameter names you may need to do some manual cleanup before it'll import and simulate correctly. Graeme![]()
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Fixing Process Antenna Violations using Nanoroute
Hi, I am getting 47 Process Antenna Violations after routing my design, all these violations are on intermediate layers. When I try to run Nanoroute(modes mentioned below), it does not adds any antenna diode to fix the violations, please suggest how to clean these violations using Nanoroute. -dbAdjustAutoViaWeight true # bool, default=true -dbAllowInstanceOverlaps false # bool, default=false -dbIgnoreFollowPinShape false # bool, default=false -dbProcessNode {} # string, default="" -dbRcExtractionCorner {} # string, default="" -dbSkipAnalog false # bool, default=false -dbViaWeight {} # string, default="" -drouteAntennaEcoListFile {} # string, default="" -drouteAutoStop true # bool, default=true -drouteEndIteration 0 # int, default=0 -drouteFixAntenna true # bool, default=true, user setting -drouteFixViaDensityViolationAfterViaSwap false # bool, default=false -drouteMaskOnlyOnLayer false # string, default=false -drouteMinLengthForWireSpreading 0 # string, default=0 -drouteMinLengthForWireWidening 1 # float, default=1 -drouteMinSlackForWireOptimization 0 # float, default=0 -drouteNoTaperInLayers {} # string, default="" -drouteNoTaperOnOutputPin false # ternary, default=false -drouteOnGridOnly none # string, default=none -droutePostRouteLithoRepair false # bool, default=false -droutePostRouteSpreadWire 1 # string, default=auto, user setting -droutePostRouteSwapVia false # string, default=false -droutePostRouteSwapViaPriority auto # string, default=auto -droutePostRouteWidenWire none # string, default=none -droutePostRouteWidenWireRule {} # string, default="" -drouteSearchAndRepair true # bool, default=true -drouteSignOffEffort high # string, default=high -drouteStartIteration 0 # int, default=0, user setting, obsoleteWarn -drouteUseMultiCutViaEffort low # string, default=low -envNumberFailLimit 0 # int, default=0 -envNumberProcessor 1 # int, default=1 -envNumberWarningLimit 0 # int, default=0 -envThirdPartyData false # bool, default=false -hfrouteConstraintFile {} # string, default="" -hfrouteConstraintGroups {} # string, default="" -hfrouteMatchReportFile {} # string, default="" -hfrouteNumReserveLayers 1 # int, default=1 -hfrouteRemoveFloatingShield false # bool, default=false -hfrouteSearchRepair false # string, default=false -hfrouteShieldTrimLength 0 # float, default=0 -routeAllowPinAsFeedthrough true # string, default=true -routeAntennaCellName ANTENNA_T3_12T_DG24RVT # string, default="", user setting -routeAntennaPinLimit 1000 # int, default=1000 -routeBottomRoutingLayer 0 # int, default=0 -routeConcurrentMinimizeViaCountEffort medium # string, default=medium -routeConnectToBump false # bool, default=false -routeDesignFixClockNets false # bool, default=false -routeDesignRouteClockNetsFirst true # bool, default=true -routeEnableNdrSiLimitLength false # string, default=false -routeEnforceNdrOnSpecialNetWire false # string, default=false -routeExtraViaEnclosure 0 # float, default=0 -routeFixTopLayerAntenna true # bool, default=true -routeHonorPowerDomain false # bool, default=false -routeIgnoreAntennaTopCellPin true # bool, default=true -routeInsertAntennaDiode true # bool, default=false, user setting -routeInsertDiodeForClockNets false # bool, default=false -routeRelaxedNdrSpacingToPGNets none # string, default=none -routeReserveSpaceForMultiCut false # bool, default=false -routeReverseDirection {} # string, default="" -routeSelectedNetOnly false # bool, default=false -routeShieldCrosstieOffset {} # string, default="" -routeStrictlyHonorNonDefaultRule false # string, default=false -routeStripeLayerRange {} # string, default="" -routeTieNetToShape auto # string, default=auto -routeTopRoutingLayer 0 # int, default=0 -routeTrimPullBackDistanceFromBoundary {} # string, default="" -routeTrunkWithClusterTargetSize 1 # int, default=1 -routeUnconnectedPorts false # bool, default=false -routeWithEco true # bool, default=false, user setting -routeWithLithoDriven false # bool, default=false -routeWithSiDriven false # bool, default=false, user setting -routeWithSiPostRouteFix false # bool, default=false, user setting, private -routeWithTimingDriven false # bool, default=false, user setting -routeWithViaInPin false # string, default=false -routeWithViaInPinSingleMask false # bool, default=false -routeWithViaOnlyForMacroCellPin false # string, default=false -routeWithViaOnlyForStandardCellPin false # string, default=false -timingEngine CTE # string, default=CTE, user setting, private Thanks Utkarsh![]()
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Amplitude sweep in VERILOG-A environment to generate multiple Output files through the Verilog-A code
I am doing a simulation in Cadence for a Delta-Sigma ADC with blocks like op-amp and Quantizer modeled in Verilog-A environment . The quantizer is a single-bit quantizer and hence modelled just as a comparator that works on a clock with V(out) = +1 when the V(in) > 0 and V(out) = -1 when the V(in) < 0. In the quantizer block, I have a c ode piece that does a file export in .dat format (@filecheck (path of the destination to store the file)). This is performed because I will load this file generated into Matlab and verify the performance metrics like SNR and IBN through the code run in Matlab. Now I want to sweep that amplitude lets say for 100 levels between a minimum and maximum. With this, I would like to generate 100 file outputs on each iteration such that I can load that in Matlab using an iteration of 100 levels. How can I modify the Verilog-A code so as to generate each file at each amplitude iteration without just replacing the existing file each time ?![]()
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RE: Sub Menus are too large
Already tried all of these options...![]()
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RE: Sub Menus are too large
Yes![]()
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