Not supported. We tend to use "n" at the end of a signal to indicate such as "CLK_ENABLEn"![]()
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RE: add bar over net alias name in capture
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RE: How to draw a closed ring with rodCreatePath
Hi, I don't think you can do that in the layout editor. If you start to draw your path a 0:0 and then place your last point again at 0:0 then that last point will actually become (0:0+width). Try it out,- create such a path in VLE and then look at it's point in the property editor. So this is not a rodCreatePath(..) issue, it's simply something a path doesn't allow. Max![]()
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Why the HB analysis PXF results are varying with TSTAB period (after sufficient steady state reach time)
Dear All, I am running a ring-oscillator with almost sinusoidal voltage output. I am injecting the PAC current at certain point and seeing the PXF result for the oscillator output voltage. I see the oscillator reaches the steady state after 1 ns. But, the PXF magnitudes for various sidebands are varying as I change the TSTAB from 2ns to 5 ns. Can anybody please tell why it is doing so ? Kind Regards,![]()
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RE: Why the HB analysis PXF results are varying with TSTAB period (after sufficient steady state reach time)
Without seeing it, I can't say (you should contact customer support). There may be something wrong with the setup and it may be reaching false convergence because of that. Andrew.![]()
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RE: How to draw a closed ring with rodCreatePath
Max is right - the path would be re-entrant (self-overlapping). You can draw it using this: rodCreatePath( ?cvId cv ?layer list("active" "drawing") ?width width ?endType "extend" ?pts list( 0:0 length:0 length:height 0:height 0:width )) Note the final coordinate is slightly different to allow for the extensions and to avoid the overlap. Andrew.![]()
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RE: Virtuoso: how to create a (truly) parametric component (i.e. with "dynamic" termOrder)?
Jorge, See this example in an article that I wrote: How to create a VerilogA model of a DAC with a variable width bus input It's slightly complicated because of the need for a pcell for the symbol and "shadow" database in the VerilogA view, but the article explains how to do that with a worked example. Regards, Andrew.![]()
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Laser Via - Buried Via
One of our layouts slipped through with a laser via on top of a buried via (fab house caught it). I don't understand why the system didn't flag it. We had BB via stagger set at 0.3837mm, and via-to-via spacing set at 0.1mm. I've been experimenting with the pad-pad connect settings, but unless I set it at 'All Allowed', I get tons of non-errors. It seems like it should be a simple setting issue, but what settings do I need that to edit to get it to flag a laser via on top of buried via? Thanks for any guidance.![]()
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RE: Laser Via - Buried Via
Sorry, meant to say "what setting do I need to edit to make the system flag a laser via on top of a buried via?" Thanks.![]()
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updating symbols
hello what would be the best way to update a symbol? i removed a few pins from the existing symbol on the current design. so "refresh symbol" gives me an error and does not work. this is how i do but if there is a better way, i would like to know. 1. export out the symbol and netlist from the design. 2. modify the symbol by removing pins and save it as a different dra file name. 3. create a psm file and a device file. 4. remove the old symbol from the design and place the new symbol manually. 5. on the parts list, remove the old symbol and add the new symbol and refdes. 6. assign the refdes to the new symbol. 7. modify the netlist using the new symbol name and import the netlist to the design.![]()
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RE: silkscreen not associated with a pcb symbol
the code below will create external drc flags on "package geometry" items that do not have a parent object/symbol owner: procedure((Find_Orphans) let((errcnt llx lly urx ury center_x center_y layer dbid) (errcnt = 0) ;; process top side (axlClearSelSet) (axlVisibleDesign nil) (axlVisibleLayer "PACKAGE GEOMETRY" t) (axlSetFindFilter ?enabled (list "noall" "lines" "shapes" "text") ?onButtons (list "lines" "shapes" "text")) (axlAddSelectAll) foreach(obj axlGetSelSet() unless((obj->parent) (llx = caar(obj->bBox)) (urx = caadr(obj->bBox)) (ury = cadadr(obj->bBox)) (lly = cadar(obj->bBox)) (center_x = (((urx - llx) / 2) + llx)) (center_y = (((ury - lly) / 2) + lly)) if(nindex(upperCase(obj->layer) "_TOP") then (layer = "Drc Error Class/Package_Top") else (layer = "Drc Error Class/Package_Bottom") ) (dbid = axlDBCreateExternalDRC("Orphan Object" (center_x:center_y) layer list(obj) nil nil)) when(dbid (axlHighlightObject car(dbid) nil) ) (errcnt++) ) ) ;; done axlMsgPut("%d DRC flags added" errcnt) ) ) axlCmdRegister( "find_orphans" 'Find_Orphans ?cmdType "general")![]()
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RE: SPB17.2: Did Capture OLB Format Change?
This appears to be an undocumented "feature". I ended up creating two sets of .OLB library files, one for V17.2 and another for V9+. Seems you can save the .SCH file to the older version ... but not the .OLBs. This is frustrating, particularly since I've been using OrCAD Capture since the DOS days.![]()
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Whiteboard Wednesdays - An Intuitive Introduction to Finite Element Analysis (FEA) for Electrical Engineers, Part 2
In this week's Whiteboard Wednesdays video, Tom Hackett continues his introduction to finite element analysis (FEA) and the important role it can play in electronics deign. For a detailed explanation of the mathematics behind Finite Element Analysis, see this excellent video by Grasp Engineering: Practical Introduction and Basics of Finite Element Analysis www.youtube.com/watch![]()
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DESIGN ENTRY CIS RENUMBERING?
TWO QUESTIONS HERE: I would like to renumber REFDES on schematic pages, but I want to start at specific number on each page. For example, I want all parts on page 1 to be x100 and up, I want parts on page 2 to be x200 and up, so-on. I want to understand how to re-enable “hole filling” on REFDES. This is a feature that USED to work, now is not working. Defined as if I have capacitors on pages honoring the numbering system in design from above (page 1 = x100-x199; page 2 = x200-x299, so on) if I want the next USABLE number on a copied part from page 1 (say R125), I place it, I want the next number in 100 range, NOT next part number in design. Again, this used to work fine, then it broke. Any help would be great! Thx![]()
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RE: Laser Via - Buried Via
i assume you want to find the stacked via locations. this skill code might help you. https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000006Ak17UAC&pageName=ArticleContent![]()
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Error in importing Netlist
Hi, While importing logic from cadence design entry hdl, I got an error as shown below Schematic supports automatically creating XNets using DML but the Layout will not automatically create any XNets. Change setting in Layout or Schematic, re-generate files, and re-run the flow. How to resolve this issue? Thanks in advance!![]()
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RE: Laser Via - Buried Via
I had raised this issue on the forum around 9-12 months ago and never got a real answer. I was using 16.6 at the time and if the laser via was exactly on the same coordinate as the mechanical via it did not trigger a DRC no matter what setting I did. If it was off just by a small amount it would trigger so I suspect the software allows this since some fabricators are ok with zero offset. All that said, the way I found was to run a via location extract and parse it in Excel for like coordinates...sigh. Which version and license level do you run? It might be a higher license level that can find this...![]()
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RE: DESIGN ENTRY CIS RENUMBERING?
1. I don't normally do this but I think this can be found in the annotation tool under "Advanced..." 1. Not seen OrCAD not use last_ref_des+1 in a while so perhaps someone with experience can speak to this...![]()
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RE: how to use ADE_L to plot waveform after command line simulation
Dear andrew, I want to know can i do the simulations of the ADE L using BASH script and provide all types of analysis with different sweeps and corners. Please help and thanks in advance. Lokesh![]()
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What battery for 30lb trolling motor?
Hello everyone,, I recently purchased a intex mariner 4 (10 ft) and am looking to add a 30lb Minn Kota trolling motor to it. I'd like to use this lightweight boat for rivers and ponds at maximum thrust. I understand that a deep cycle battery is needed but what size would you recommend? According to Amazon, most people paired it with a 30ah battery. The motor is rated for around 30amp draw, would that mean this battery would only last best trolling motor batteries for one hour at full speed under ideal conditions? I'm looking to be able to be on the water all day at decent speeds. Any input would be appreciated LB.![]()
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Send dc match results to the outputs
Hello everyone,, I wonder if there's a possibility of sending the results of a dc match simulation directly to the ADE-L outputs window. Typically, a summary of the dc match results can be seen in the output log of the simulation, but it would be really convenient to be able to see the mismatch result directly as is done with other measurements coming from stb analysis via results > Direct Plot > main form. In any case, if there's an alternative way to do so I'd be thankful if you can share it here. Regards, LB![]()
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