I use the "ibis_buffer" component of analog Library "analogLib" to verify my IBIS model of a 3-state output buffer. The IBIS data is included by file. My testbench includes this ibis_buffer and the original 3-state output buffer from which the IBIS data was gained from, to compare the two. Each of then has a transmission line and load model connected to the output, of the same type and parametric values, of course. Both have their output are enabled. The waveforms have the same shape, yet the delays are incorrect. When using a very slow ramp at the stimulus input, I can see that the IBIS buffer model switches at a different voltage (say, 0.7 V for the IBIS buffer and 0.9 V for the real component and for the rising edge, and at 0.3 V for the IBIS model and 0.9 V for the real component for the falling edge). Yet the IBIS data has been gathered at the correct switching thresholds. (The effect being that the IBIS waveform's rising edge comes too early, and the falling edge too late, therefore the duty cycle is also different, the postive pulse is wider for the IBIS model than for the real component.) - What switching thresholds can I expect the ibis_buffer component to use? - How can I adjust it (if at all)? - Is there any documentation available for download, like the "Spectre IBIS Appnote http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/Spectre_IBIS_AN.pdf " quoted in a very old post from 12 years ago (at https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/2818/running-ibis-model-file-in-spectre) or the Article 11446874, "How to include and simulate IBIS buffer models in ADE which include package parasitics?" from the same post, both unfortunately not being available anymore (dead link, no search results). Thank you very much.![]()
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Switching threshold of ibis_buffer
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RE: ADE-XL retrieve values and calculate min
Pedro, This appears to be a bug. I filed CCR 2165705 to get this fixed in ADE Assembler (we may not fix it in ADE XL since ADE XL is in "sunset" mode). You might want to report this to customer support too and ask for a duplicate CCR to be filed. It seems that using Plot All, Plot across Corners (not sure why that's even available for a MAC expression) and Plot across Design Points all plot exactly the same way - versus the Design_Point, and I think Plot All should plot against the swept variable (even if it's discrete points). Regards, Andrew.![]()
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RE: What is the difference between DC operating parameters ron and gds of MOS
Hello RFStuff, it depends on the terminology of your small signal equivalent. I added a Small signal equivalent that i use and the equations that came from it,shown bellow. There is no Ron or gds in it. If its Ok with Andrew ,can you share the small signal equivalent you are using, so we could find the formulas for ron gds, as the shown bellow parameters where found.![]()
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RE: What is the difference between DC operating parameters ron and gds of MOS
Actually, they're not quite the same. It depends a bit on the model, but if you look at (say) the bsim4 chapter of the Spectre Circuit Simulator Components and Device Models Reference manual ( /doc/spectremod/spectremod.pdf) then there are hyperlinks to the equation for gds (12-31 in the Spectre 19.1 documentation) whereas ron is vds/ids (so gds is the small signal conductance, whereas ron is the large-signal resistance at the operating point). I don't think RFstuff's question is related to which small signal equivalent he/she is using - the question is related to the operating point numbers that are produced by spectre. Regards, Andrew![]()
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RE: region annotation on mosfet
Hello Andrew ,It works ,Thank you very much. Before running DC simulation. Results->Annotate->DC Operating Point from ADE ,then i made sure DC operating point data is save and ran DC simulation. After that operating point parameters where not grey and it worked as shown bellow.![]()
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Regarding changing pf standard Jedec types that are available in allegro PCB Librarian
My question is how can we change a standard JEDEC Type that is available with respect to its dimensions to make a custom library.![]()
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RE: How to capture the Sampled PAC/PXF results at a given frequency/sideband using OCEAN command.
Yes. That result will be complex by the way, so you may need to use mag() around the entire thing. BTW, you can also use: out=v("/out" ?result 'pac_sampled) sweepValues(out) ; this will give you a list of the eventtime values so you don't have to guess the time of the event Andrew.![]()
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RE: How to capture the Sampled PAC/PXF results at a given frequency/sideband using OCEAN command.
Thanks a lot Andrew.![]()
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RE: What is the difference between DC operating parameters ron and gds of MOS
Thanks a lot robert21 and Andrew.![]()
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how to create a waveform for each simulation corner with an Ocean script and send it back to ADEXL
Hi All, I'm running simulation with ADEXL at different corner, and for every corner there is a csv file generated, containing simulation data results. with an ocean script that I include in the ADEXL outputs setup, i'm reading the files generated at each simulation run at the end of the simulation, and then I generate a waveform from each of those files with the ocean script. Unfortunately it seems like the script reads the file generated at the first corner and then uses the same file for all the other corners thus generating the same waveform for each corner. Is there a way to tell the script to run on different corner? here below is my script Regards Frantz print("start my ocean script") if( axlGetCornerNameForCurrentPointInRun() then ccorner = axlGetCornerNameForCurrentPointInRun() else ccorner = "TT_85" ) ; if i'm running only one corner i set the corner name to the default's one path = "simulation_path" sprintf(file_toread "%ssbr_norm_%s.csv" path ccorner) fr = infile(file_toread) when( fr while( gets(nextline fr) i++ ;I'm counting the number of lines in the files ) ) Nlines = i i = 0 j = 0 close(fr) declare( Val[Nlines-1]) ; I declare a vector to save all the data in the file tsteps = VAR("tstep") tend_plot = tsteps*(Nlines-1) tarray = linRg(0 tend_plot tsteps) ; I create a time axis aList1 = '() ; I create a list to save all the data from the file fr = infile(file_toread) gets(nextline fr) for(i 1 Nlines for( j 1 Ntot_taps_rk12 fscanf(fr "%f %s" val1 col) sum++ if(sum == 10 then aList1 = cons(val1 aList1 ) ) ) sum = 0 ) tax = drCreateVec('double tarray) ; i create the time axis on the x tax -> units = "s" ; i create the label of the x axis yax = drCreateVec('double aList_rk1) ; i create the y axis using the data read from the file yax -> units = "V" adxel_wave_form = drCreateWaveform(tax yax); I create the waveform to be brought out on the adexl gui axlAddOutputs(list(" adxel_wave_form ")) axlOutputResult( adxel_wave_form " adxel_wave_form ") ; I bring the waveform into adexl outputs close(fr) print("finished my ocean script")![]()
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TSMC OIP: Process Status
Last week was TSMC's Open Innovation Platform Innovation Forum (aka OIP). Dave Keller welcomed everyone and then introduced Cliff Hou who gave the update on everything technical. Here's what he said. Or rather, here's what I think he said. I will give my usual caveat at the start of posts like this: TSMC does not allow photography, video, or recording the presentations, and they don't provide the slides. So this is entirely from the notes I took during the presentation. I realize that this post is fairly dry and dense with numbers and dates, but since TSMC is far and away the largest foundry, these details are important, and they are not available anywhere else. You can try and find out from TSMC's website something specific like when N6 risk production is planned to start...but you will discover the information is not there. Whenever processes are compared below I say things like "NX is 15% faster than NY, 30% less power". This means that you can get a speed increase of 15% at the same power, or a power reduction of 30% at the same performance. It does not mean you can get both at the same time. Obviously, you can also blend the two and take a part of the improved process as a performance increase and a part as power reduction. N5 N5 (5nm) value proposition is that it is optimized for both mobile and HPC with innovative scaling features. Risk production started in March 2019. It will be followed by N5P (P for performance) with risk production starting a year after N5, so that would be about March 2020. Comparing N5 to N7, it is 15% faster, 30% lower power. Logic density is 1.8X, SRAM scaling is 0.75, analog scaling around 0.85. Key features of N5 is that it is fully-fledged EUV adoption, which reduces cycle time due to fewer steps that multi-pattern everything. It is enhanced with a transistor with a high-mobility channel for both performance and power. There are other architectural features that enable logic and SRAM density scaling. There are low-resistance contacts and vias. The I/O transistor can be either 1.5V or 1.2V. N5 HPC has extreme Vt LVT device that is 25% faster than N7. The HPC standard-cell library has optimized metal and a via pillar array to further boost performance by 10%. There is a special device offering to enable 112Gbps SerDes. For decap capacitors, there is a super high desngith MIM (SHDMIK) that provides 4X more decap than HDMIM (MIM stands for metal-insulator-metal, since these capacitors are built in the BEOL in the metal stack). The increase in decap results in an extra 4% speed boost at the same voltage. For analog, TSMC have taken a new approach with N5 Restricted Design Rules (RDR). They have provided an analog cell library that goes beyond just providing transistors in the PDK. This improves the manufacturing window.. The analog cells are transistors in abuttable layout templates with predefined cell-heights and pre-drawn layout patterns for the m0 layer and below. Each transistor is surrounded by predefined and validate technology. It achieves much better SPICE to silicon correlation than the non-RDR approach. To build an analog block, you build the schematic using these cells instead of transistors, then route the metal layers on top after placement. Finally, add the guard-ring and boundary cells for a final DRC-clean design. Cliff had some nice pictures of some blocks designed this way for LPDDR4, PHY, PLL, DAC, and so on. But since I wasn't allowed to take pictures I can't show you. N5 IP status is that all the foundation for mobile and HPC has been silicon validated. Key mobile IP has been silicon validated. HPC is having first tapeouts. N7 N7 compared to 16FF+ is 30% faster, 55% reduction in power, 3.3X increase in logic density, 0.38X SRAM area. Mass production started in April 2018. It was the fastest technology ramp in TSMC's history, beating even the N10 technology ramp. All IP is available. N6 N6 is a die cost reduction from N7 by increased use of EUV to reduce process complexity (and improve cycle time), and improve logic density by 18%, making use of CPODE (continuous poly on diffusion edge). Risk production starts in Q1 2020. There is a yield improvement from the smaller die size and the reduction in layers. If you simply want to take an N7 design and get the benefits of N6, you can just do that. It has compatible design rules, SPICE, and IP libraries with N7. Alternatively, you can use improve N6 logic blocks along with reusing N7 IP for everything else (in particular SRAM). N6 logic density is 1.18X versus N7 (using an Arm Cortex-A72 as a test vehicle). Cerebras Next, Cliff invited Dhiraj Mallick of Cerebras Systems to come and talk about the wafer-scale deep learning "chip". I put chip in quotes since this is the largest square die it is possible to manufacture on a 300mm wafer. As Dhiraj said "we announced this last month at HOT CHIPS". As it happens, I was there and I wrote about it a few days later. Most of what he said at OIP was a repeat of what Cerebras said at HOT CHIPS, so read my post HOT CHIPS: The Biggest Chip in the World . The chip was manufactured in TSMC 16nm. There was very tight coupling of the engineers in TSMC's Fab 14 with Cerebras's physical design team, where they tried various new ideas and built test chips to qualify the process. The big challenge was to build reliable connections from die to die across the scribe lines since the manufacturing process still required a reticle to be repeated across the wafer, even though it was going to be left whole and not cut up later. Specialty Technology Cliff came back to talk about low power and RF. 22ULL low Vdd (note: 22ULL low Vdd is a process name, not the same as 22ULL) is a solution with Vdd down to 0.6V for IoT applications. 28HPC+ power is down 20% to 22ULL and then another 45% down to 22ULL Low Vdd. The design flow is the same but there are large variation challenges for library characterization and timing signoff, so a deep understanding of variation is required during synthesis and physical design. For RF transceivers and WiFi there is 28HPC/RF and 22ULP/ULL/RF already in production. 16FFC/RF enhancement 1 is ready today, N7/RF will come in 2H 2020. There is a big power reduction from 28 to 16 and another big one to 7. N16FFC/RF enhancement 1 has new RF transistors and design kits are developed with higher Ft and Fmax. It goes up to 300GHz. For mmWave, 28 and 22 are in production, and there will be 16FFC/RF enhancement 1. There is also a second 16FFC/RF enhancement 2 with new transistors that takes Fmax up to 400GHz. It will be ready in Q2 2020 (SPICE and PDK in Q1). For RF SOI there is 0.13SOI in production today, with a coming enhancement 1 ready in Q1 2020. After that there will be N40SOI. With 0.13 can go to 120GHz, with enhancement 1 it will go to 150GHz, and with N40 to 220GHz. N40RF is SOI with air gap. 3D Packaging Next Cliff moved on to packaging. TSMC has two basic technologies called InFO (integrated fanout) and CoWoS (chip on wafer on substrate). CoWoS is targeted at very large designs. Currently they can do designs 1.5X the reticle size, in 2020 that will go to 2X and in 2021 to 3X reticle size. They can do wafer on wafer (WoW) and chip on wafer (CoW). Obviously WoW requires the die size to be identical and the yield to be very high (since any bad die takes out its opposite number too). For CoW they can only use known good die (KGD) that have already been tested. There is a whole 3D-IC design flow to stack die during verification, perform IR/EM analysis, thermal, signal and power integrity, and more. On the day of OIP, TSMC had announced a 4GHz CoWoS HPC chiplet-based design, proven in silicon, around an Arm Cortex-A72 and using low-swing 0.3V I/O design that achieved 8Gb/s per pin, giving a total of 320GB/s. Summary Cliff's summary: N5 is ready, risk production started in March, they are receiving customer product tapeouts. TSMC is continuing to advance new technology with N7 going to N6, N16 going to N12, N28 going to N22. TSMC has a comprehensive RF platform. Comprehensive 3D-IC design ecosystem to enable product innovation. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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Include external information/procedure in PCell
Hello, Situation : I have created a PCell that generates a (transformer) layout based on the parameters. All custom procedures are included (as lambda functions) inside the PCell body. Currently, technology related information (which layers to use, etc.) is embedded in the body, the parameter default values (layer/metalstack options) as well as the cdf default values. I would like to extract that information and move it into a dedicated file or at least a single place in the file. Thereby, it should be much easier porting the PCell to a different technology. Furthermore, I would like to use some of the included functions/code in a different PCell. Currently, I just duplicate the code, but that is very annoying for code maintenance. Issue : If I move the information or these functions outside the PCell definition into separate procedures, it only works as long as they are loaded. Loading them in the CIW does not work for streaming out (for DRC etc.). Do you have any idea how I could: a ) Copy/Attach already defined code to the PCell. How this is meant: I define a procedure/lambda function and somehow pass it to pcDefinePCe ll so it can be used in the body without loading the procedure again. OR if this does not work b ) Specify a script that is always loaded when the PCell is evaluated There is .cdsinit , but as far as I know that is only for the graphical tools. There is libInit.il included in the PDK, but I don't think me (or the technology manager) can/should modify it. Thank you very much for any input. Using Virtuoso ICADV12.2![]()
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How to control AMS waveform data compression
Hello, I am running a long top level AMS simulation, saving a lot of signals across multiple hierarchies. Most of the signals are used just for checking functionality, but on a few of them I want to to measure performance, so I need a descent accuracy for them. I use the Compression feature (in transient options) to reduce the output file, and it works great for the majority of the signals - database is significantly smaller. But for those few signals that I need good accuracy - the compression is removing too much of the data that I can't get the accuracy I need. I tried adjusting compvabstol / compiabstol but I see no improvement, the changes in the signals are larger than those thresholds so I'm confused to why it's not saving more points. This happens with both currents and voltages. Is there a way to tell AMS simulator what signals not to compress? Are there any other knobs I should try? Thanks, Tomer![]()
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Virtuoso DEF import creates incorrect pathseg widths
I have a DEF coming from ICC and when I import the wires do not get created at the correct widths. For instance, the DEF specifies UNITS DISTANCE MICRONS 4000 ; + LAYER m2 WIDTH 104 SPACING 80 But when my design is imported all m2 paths are width 0.025um instead of 0.026um. Is this due to an override in my techfile or something? I have similar issues in other metal layers as well, and it seems to be affecting all wires. for technical info: # IC Compiler II write_def # Release : P-2019.03-SP2 VERSION 5.8 ; Virtuoso version ICADVM18.1-64b.500.4![]()
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Incorrect multiplier in Spice In
Hi, I used Spice In to import SPICE netlist to generate schematic in IC181 (version ICADVM18.1-64b.500.4). The technology is in tsmcN16 and library is defined in cds.lib. Schematic was generated without any error. However, it failed LVS due to the incorrect number of multiplier. Original SPICE netlist: M_0 nn2 net122 VSS VSS nch_18_mac l=150.0n nfin=15 m=18 spiceIn.log: Inst: M_0 Created net 'nn2'. Created net 'net122'. Found net 'VSS'. Found net 'VSS'. Created net 'nch_18_mac'. Master Cell: 'nch_18_mac'. Master Cellview: 'tsmcN16.nch_18_mac:symbol' found. Created instance 'M_0'. Created connection between net 'nn2' and term 'D'. Created connection between net 'net122' and term 'G'. Created connection between net 'VSS' and term 'S'. Created connection between net 'VSS' and term 'B'. Created propName='model'; propType='string'; propVal='nch_18_mac'. Created propName='l'; propType='string'; propVal='1.5e-07'. Created propName='nfin'; propType='string'; propVal='15'. Created propName='m'; propType='string'; propVal=' 18 '. LVS netlist: MM_0 nn2 net122 VSS VSS nch_18_mac l=1.5e-07 nfin=15 m=1 Is there any solution for this issue? Please let me know if there is any existing solution or discussion about this issue. Thanks.![]()
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When using the difference layer name between captable and tech lef
Hello. I would like to ask for help. I'm using EDI(v14), some layer name is different between captable and tech lef. For example, in captable : Metal1, M12C, Metal2, M23C, Metal3, ... in tech lef file : M1, V1, M2, V2, M3 .... Will EDI automatically recognize each as the same layer?![]()
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RE: PSS convergence issue when Chopper(implented using NMOS) kept at low impedance node
Hi Andrew I could not make a new question in forum and ask my question in here. I am simulate a dc dc converter using periodic steady state tab. I set tstab such that the converter settles in steady state. but after just one iteration simulation stops withno error and warning![]()
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add bar over net alias name in capture
how to add bar over net alias name in capture something like we do for pin name.![]()
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RE: Clear silkscreen from pins in Allegro Package
Hi Dave, we need to custom spacing of clearPiSilk. how can I do ? Please help us.![]()
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Schemetic library and Package library
For cadence, does integrated library exist for schematic and PCB design? Where can I download integrated library? If integrated librar does not exist, where can I download Schemetic library and Package library? Thank you![]()
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