The Cadence® Quantus Smart View is the next generation of the Extracted View in the Virtuoso environment. The Smart View provides the same functionality as the Extracted View, but it uses a highly efficient and scalable storage mechanism. This means that Smart View can manage larger, more complex designs at advanced nodes with a reduced overall extraction run time and netlist size. In fact, the Smart View not only helps with faster netlist generation in Virtuoso® ADE Assembler and Virtuoso® ADE Explorer , you can also use it to view the parasitics in the layout within a desired threshold and also their net fragment names. You can also use the Smart View properties to analyze values and connectivity details of extracted parasitic elements. Click here to download the Using Quantus Smart View in the Virtuoso Analog Design Environment Rapid Adoption Kit or search for it on Cadence Online Support . This details how to: Create a Smart View Set up ADE to use Smart Views Perform in and out-of-context Probing Display Parasitics in Layout Create Parasitic Reports There is also a video to see all of this in action, but I'll outline the main features below. . Out of Context Probing A key benefit of using Smart View is the ability to automatically map information from the schematic name space to the post-layout(Smart View) name space. This means that you can reuse expressions created with schematic net and terminal names when simulating the Smart View and those net and terminal names will automatically be mapped to their equivalent post-layout names. The TRAN test in this plot was simulated using the schematic view, the TRAN_EXTR_SV test was simulated using the Smart View. Using Direct Plot to select a terminal on the schematic from the TRAN_EXTR_SV test will plot the current from the Smart View without any need for user mapping. . In Context Probing Using Direct Plot to descend into the Smart View will open Virtuoso® Layout Suite . You can select a net in the Layout XL Navigator and select which terminals to plot. . Displaying Parasitics You can also just open the Smart View, choose Display Parasitics from the Smart-Parasitics menu. Here, you can toggle to view either the resistance or capacitance parasitics or both and choose the minimum and maximum thresholds. You can also choose to see the Node Names for the net fragments. Zooming right into the parasitcs, you can see the parasitic values and the net fragment names. . Overlaying the Layout You can choose the Smart-Parasitics->Overlay Layout option to display the layout view in the background while keeping the Smart View in the foreground. . Parasitic Reporting With the integration of Smart View in Virtuoso, how you view parasitics going forward in Virtuoso is certainly set to change forever. But, what is not meant to change is the quick and easy way you have always been able to report parasitics. With Smart View too, you can report parasitics as efficiently as with Extracted View. Simply change the Extracted View in the Parasitic Setup form to point to the Smart View! . Related Resources Rapid Adoption Kit Using Quantus Smart View in the Virtuoso Analog Design Environment RAK Video Using Smart View in the ADE Flow User Guides Virtuoso ADE Assembler User Guide Virtuoso ADE Explorer User Guide Quantus QRC Extraction Users Manual Virtuoso Layout Suite XL User Guide Virtuoso Parasitic Aware Design User Guide For more information on Cadence circuit design products and services, visit www.cadence.com. About Virtuosity Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts. Happy Reading! Arja![]()
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Virtuosity: A Smart Extracted View
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Verifying Power Intent in Analog and Mixed-Signal Designs Using Formal Methods
Analog and Mixed-signal (AMS) designs are increasingly using active power management to minimize power consumption. Typical mixed-signal design uses several power domains and operate in a dozen or more power modes including multiple functional, standby and test modes. To save power, parts of design not active in a mode are shut down or may operate at reduced supply voltage when high performance is not required. These and other low power techniques are applied on both analog and digital parts of the design. Digital designers capture power intent in standard formats like Common Power Format (CPF), IEEE1801 (aka Unified Power Format or UPF) or Liberty and apply it top-down throughout design, verification and implementation flows. Analog parts are often designed bottom-up in schematic without upfront defined power intent. Verifying that low power intent is implemented correctly in mixed-signal design is very challenging. If not discovered early, errors like wrongly connected power nets, missing level shifters or isolations cells can cause costly rework or even silicon re-spin. Mixed-signal designers rely on simulation for functional verification. Although still necessary for electrical and performance verification, running simulation on so many power modes is not an effective verification method to discover low power errors. It would be nice to augment simulation with formal low power verification but a specification of power intent for analog/mixed-signal blocs is missing. So how do we obtain it? Can we “extract” it from already built analog circuit? Fortunately, yes we can, and we will describe an automated way to do so! Virtuoso Power Manager is new tool released in the Virtuoso IC6.1.8 platform which is capable of managing power intent in an Analog/MS design which is captured in Virtuoso Schematic Editor. In setup phase, the user identifies power and ground nets and registers special devices like level shifters and isolation cells. The user has the option to import power intent into IEEE1801 format, applicable for top level or any of the blocks in design. Virtuoso Power Manager uses this information to traverse the schematic and extract complete power intent for the entire design. In the final stage, Virtuoso Power Manager exports the power intent in IEEE1801 format as an input to the formal verification tool (Cadence Conformal-LP) for static verification of power intent. Cadence and Infineon have been collaborating on the requirements and validation of the Virtuoso Power Manager tool and Low Power verification solution on real designs. A summary of collaboration results were presented at the DVCon conference in Munich, in October of 2018. Please look for the paper in the conference proceedings for more details. Alternately, can view our Cadence webinar on Verifying Low-Power Intent in Mixed-Signal Design Using Formal Method for more information.![]()
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Simulation of LPDDR4X Interface: What Designers Need to Know and Do
System designers are familiar with standard DDR4 RAM components but with the demands on increasing performance and decreasing power consumption in mobile products, LPDDR4 and its variation, LPDDR4X, have become the desired memory devices for in-vehicle infotainment, smartphones, tablets, and thin notebooks. Understanding the design specifications for LPDDR4 and LPDDR4X devices and their application conditions is critical to achieving successful system-level designs. Like DDR4 memory requirements, the performance of LPDDR4 is measured by eye mask, jitter, and BER. In addition, LPDDR4 and 4X interfaces specify these measurements to both the data and address signals, with LPDDR4X operating at the I/O supply voltage reduced by 55%. When evaluating and implementing a DDR4/LPDDR4/LPDDR4X interface in a system, designers face additional challenges in modeling and analyzing the memory subsystem besides the normal Signal Integrity (SI) and Power Integrity (PI) considerations. For example, BER measurements using serial link analysis techniques can only be achieved on individual channels of differential signals. For memory applications with parallel bus groups of single-ended signals, directly applying the channel analysis method is not enough and new methodologies need to be in place to guide design practice. In this year’s DesignCon ( DesignCon2019 ), a group of engineers at Texas Instruments shared their experience in designing and analyzing LPDDR4X interfaces in their products. Their solutions and discussions are invaluable to system designers who are looking to understand common design concerns regarding LPDDR4X: How to handle the memory controller’s requirements for the READ cycle? Memory controllers today, such as the ones provided by the Cadence IP division, are equipped with advanced features that can help with troublesome timing parameters. When applying the channel simulation method to parallel bus simulations (to meet the BER specification of LPDDR4X), designers need to understand the interconnect response in a serial link channel is different from a group of bus signals. Validating the channel simulator and circuit simulator is a necessary step in the analysis process. The biggest challenge for designers is how to proceed with a correct simulation methodology for high data rate buses. With the JEDEC specification being so complicated and many design rules/guidelines to follow, it can be a nightmare for designers to evaluate their designs and generate a DDRx measurement report. Fortunately, using Cadence provided simulation templates for data (including WRITE and READ) and address signals of LPDDR4X, designers can follow a step by step analysis process, to perform complete design analysis without missing important noise effects, such as crosstalk and power supply noises. For the details of TI’s LPDDR4 design success, visit here . Team Sigrity space Further Reading Blog: Power-Aware SI DDR4 Simulation: You Have a Choice! Blog: Chiplets -- Reinventing Systems Design LPDDR4 Complete Solution![]()
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RE: Import Schematic from Mentor Tanner to Cadence
Hi Andrew, I ran into a few problems while implementing your solutions. The following window popped up when I tried to import the EDIF. The Run Directory and Input File sections made sense to me, could you please tell me what is to be added in the other sections? Also, when I clicked on OK, this is what happened: Loading cph.cxt filename - /tmp/edifTMPm25079 fullname - /tmp/edifTMPm25079 Saving setup data to -> /tmp/edifTMPm25079. Saving setup data ok checkout of edifin (940) was successful Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.01s. *WARNING* LIB Inverter from File /home/cadence/cadence/installs/IC618/share/cdssetup/cds.lib Line 8 redefines LIB Inverter from the same file (defined earlier.) *WARNING* LIB basic from File /home/cadence/Untar/AccessRequest-TC013534_1/TN28CRSP025W1_1_0_2P2A/iPDK_CRN28HPC+_v1.0_2p2a_20170531_all/iPDK_CRN28HPC+_v1.0_2p2a_20170531/cds.lib Line 1 redefines LIB basic from File /home/cadence/cadence/installs/IC618/tools.lnx86/dfII/etc/cdsDotLibs/composer/cds.lib Insert UNDEFINE basic before DEFINE basic in /home/cadence/Untar/AccessRequest-TC013534_1/TN28CRSP025W1_1_0_2P2A/iPDK_CRN28HPC+_v1.0_2p2a_20170531_all/iPDK_CRN28HPC+_v1.0_2p2a_20170531/cds.lib Or remove or comment out DEFINE basic in /home/cadence/cadence/installs/IC618/tools.lnx86/dfII/etc/cdsDotLibs/composer/cds.lib to suppress this warning message. *WARNING* LIB analogLib from File /home/cadence/Untar/AccessRequest-TC013534_1/TN28CRSP025W1_1_0_2P2A/iPDK_CRN28HPC+_v1.0_2p2a_20170531_all/iPDK_CRN28HPC+_v1.0_2p2a_20170531/cds.lib Line 2 redefines LIB analogLib from File /home/cadence/cadence/installs/IC618/tools.lnx86/dfII/etc/cdsDotLibs/artist/cds.lib Insert UNDEFINE analogLib before DEFINE analogLib in /home/cadence/Untar/AccessRequest-TC013534_1/TN28CRSP025W1_1_0_2P2A/iPDK_CRN28HPC+_v1.0_2p2a_20170531_all/iPDK_CRN28HPC+_v1.0_2p2a_20170531/cds.lib Or remove or comment out DEFINE analogLib in /home/cadence/cadence/installs/IC618/tools.lnx86/dfII/etc/cdsDotLibs/artist/cds.lib to suppress this warning message. Process edifin Done -- check the file edifin.log for more information Here's what the log file contained : error at line :1 between 'edif' and 'Project_design' Unexpected character " " in input error on line 1: between 'edif' and 'Project_design' syntax error Translation complete. There were 0 warning messages and 2 errors in the design. I would really appreciate any suggestions that could aid me. Thanks for going through this!![]()
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RE: allegro17.2 hotfix051 Capture can't close Property Editor window with keyboard CTRL+F4
You need to post this on the Cadence support website. This is the user forum and is not for fixing bugs.![]()
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Plotting transistor parameters in a temperature sweep
I'm doing a temperature sweep using: analysis('dc ?saveOppoint t ?param "temp" ?start "-40" ?stop "120" ?step "20" ) Aside from the usual voltages and currents, is it possible to also plot an operating point aspect of a device e.g. mn1's threshold vth or transconductance gm?![]()
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RE: Plotting transistor parameters in a temperature sweep
Yes, add: saveOpPoint( "/I7/M1" ?operatingPoints "gm vth" ) This corresponds to the Outputs->To be saved->Select OP Parameters entry in ADE L. Having done that, you can then plot OS("/I7/M1" "gm") or using getData("I7.M1:gm" ?result 'dc) - unfortunately for the latter you have to use the netlist name for the component. Regards, Andrew.![]()
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RE: Import Schematic from Mentor Tanner to Cadence
Without seeing the EDIF file, this is quite hard to debug. Perhaps you can do the following two commands in UNIX: file Project_design.edf head -2 Project_design.edf | cat -vet and show me what each outputs (the second will output just the first two lines of the EDIF file, but show any unusual characters). Regards, Andrew.![]()
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RE: Fix "tool tip" colors in GNOME
Hi Jorge, I found two bits of info related to this. Not sure if either fix the problem reliably because I didn't try it myself. The first is another article: Toolbar tooltip (or mouseover popup message) fonts are hard to read" The second was a case which had this summary: I solved problem with white-on-black tooltips with 4 gtkrc files: 1. ~/.config/gtk-3.0/gtk.css /* tooltips */ @define-color tooltip_bg_color #ffffaf; @define-color tooltip_fg_color #000000; 2. ~/.config/gtk-3.0/settings.ini [Settings] gtk-color-scheme = "tooltip_bg_color:#ffffaf\ntooltip_fg_color:#000000" 3. ~/.gtkrc-2.0 include ".gtkrc-2.0-gnome-color-chooser" 4. ~/.gtkrc-2.0-gnome-color-chooser style "gnome-color-chooser-tooltips" { bg[NORMAL] = "#FFFFAF" fg[NORMAL] = "#000000" } widget "gtk-tooltip*" style "gnome-color-chooser-tooltips" http://askubuntu.com/questions/70599/how-to-change-tooltip-background-color-in-unity You can rename the /home/user/.config folder to resolve the issue.![]()
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RE: Fix "tool tip" colors in GNOME
Hi Andrew; removing the "$HOME/.config/Trolltech.conf" file solved the problem! It changed the tooltip font color to black, which has good contrast against the pink background. Thanks so much for your help! Regards, Jorge.![]()
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PVS Rule writing
Hi, How to check the length and perimeter of all the nodes by writing PVS rule. Thank you Pranay![]()
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How to select object based on shape
Hi All, I want to select the object(Pin, Via & Symbol) based on the shape. please help on this. Regards, Sakthivel![]()
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RE: Input Capacitance Characterization in Cadence Liberate
Hi Guang, one of the harness example codes in the manual is shown below: https://pastebin.com/QZrD6Xb6 1. What do " Xdriver0_1" and "I0_altos_tmp" represent ? altos_in, altos_out and altos_stim were explained in the manual. 2. In this example, the input stimulus to the target cell seems to be an inverter. But what does the "order" mentioned in number 3. imply ? Are vdd, vss and INV_1 assigned to other 3 terms respectively ? * driver for pin I1, * I1_altos_stim - > I1_altos_tmp - > I1_altos_in Xdriver1_1 I1_altos_tmp I1_altos_stim vdd vss INV_1 3. Although the cell behavior is similar to my case (un-buffered), I cannot find a diffinition of input capacitance in the cell or any .subckts. So in this case, is the input capacitance of target cell neglected or considered to be driving inverter input capacitance (Both not accurate) ? 4. Under "harness parameters", _cap definition is there for output loads. There is no way to define the input cap though ! Anuradha![]()
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Badges—Not Just for Scouts Anymore
Were you a Boy Scout? Or a Girl Guide or Girl Scout? What badges did you earn? Not the digital technology badge, to the left, since that was only introduced in 2014 to replace the computers badge. It looks like an SoC (scout-on-chip) on a small printed circuit board. I was a scout in my teens, and although I could program by then, I don't think you could get a badge for anything electronic at all. The troop I was in was more focused on hiking, caving, climbing, and other outdoor things, along with a healthy portion of community service. Would you like a badge? Did you miss out as a kid? You can now get recognized for your proficiency with Cadence tools. You don't get an actual physical badge to sew on your shirt (although I'm sure you can find someone on Etsy who'll run you up one). These are digital badges, and they look like the one on the right. You can be any of a customer, a university student, or an employee. How Do You Earn a Digital Badge? The short version: you pass a proficiency exam for the relevant tool. The longer version: You sign up for a course that has a digital badge exam. You complete the course. If it is an internet course you go at your own pace. Take the digital badge exam. This is about 50 questions, so will take an hour or an hour-and-a-half. See above for an example question (on SKILL). Complete the post-exam survey. You will then get a digital badge from Cadence. It is verified by Credly so it can always be confirmed, and it describes the course and exam you completed. If you like, you can put the badge on sites like LinkedIn too. Just not on your sleeve. Available Courses Currently, the following courses have digital badge exams. But more are being added all the time: Allegro Design Entry HDL Front-to-Back Flow v17.2 Allegro High-Speed Constraint Management v17.2-2016 Allegro PCB Editor Basic Techniques v17.2-2016 Allegro PCB Librarian v17.2 Analog Modeling with Verilog-A v17.1 Innovus Implementation System (Block) v18.1 Mixed Signal Simulations Using Spectre AMS Designer v18.03 Physical Verification System v16.1 Sigrity PowerDC Optimize PI v2018 SKILL Language for Parameterized Cells vIC6.1.7 SKILL Language Programming vIC6.1.7 Tempus Signoff Timing Analysis and Closure v18.1 Virtuoso Connectivity-Driven Layout Transition vIC6.1.7 Virtuoso Layout for Advanced Nodes: T1 Place and Route vICADV12.3 Virtuoso Layout for Advanced Nodes: T2 Electromigration vICADV12.3 Virtuoso Layout Pro: T1 Environment and Basic Commands (L) vIC6.1.7 Virtuoso Layout Pro: T2 Create and Edit Commands (L) vIC6.1.7 Virtuoso Space-Based Router Express vIC6.1.7 Virtuoso Space-Based Router vIC6.1.7 More Information For information on digital badges, see the Become Certified page. To get started, for everyone except students, register through the Learning Management System . In the US, you can also call 800-787-2460 and a real person will answer. University students go through the Cadence Academic Network. For all things training, such as course descriptions, class schedules, and the full catalog, start at the Cadence Training Page . For a printable version of much of the material, here is the 24-page pdf Training Brochure . Yes, if you want your kids to follow in your footsteps, there's a scout electronics badge. That's it to the left. The wrong type of transistor. We're more source-gate-drain people than emitter-base-collector people. But a badge with a transistor, we'll take it. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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RE: Input Capacitance Characterization in Cadence Liberate
1. Xdriver* are instance names in the actual external driver in this example. 2. The example is just to show you how to define a harness to bias/load a cell with external circuit. Actual content will depend on your case. 3. I do not see any similarity here. generally speaking, a transimisson/pass gate does not have a liberty model, as this is not documented in Liberty specification. 4. I was hoping you can use a harness to include the elements, so that the actual capacitance will be simulated during your Liberate run. Guangjun![]()
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RE: Input Capacitance Characterization in Cadence Liberate
[quote userid="178062" url="~/cadence_technology_forums/f/custom-ic-design/41182/input-capacitance-characterization-in-cadence-liberate/1359105#1359105"]4. I was hoping you can use a harness to include the elements, so that the actual capacitance will be simulated during your Liberate run.[/quote] If this cell is used for a well defined design, I can define the right output capacitance to the cell using a harness (As I know the exact capacitive load that connects to the cells output). But during the synthesis, the capacitive load to any cell bound to change, so that assigning a fixed load during a characterization does not help. Instead the "input capacitance" should be decided from kind of a look up table or something depending on the attached load. If there is a harness parameter for input cap i.e. _cap, I can directly assign out_cap to be in_cap in harness subckt block (instead of letting it to be a fixed value). May be this is not doable. Anuradha![]()
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RE: Input Capacitance Characterization in Cadence Liberate
From what I understand, the input capacitor come from contribution of other active devices. That's why I suggested you to try harness. with this approach, the devices in the harness will be included/simulated during the charatcerisation. If the input cap has fixed values depending on external port condition, you can also create a wrapper cell with the same name as the cell to be characterized. inside the wrapper, you can use spice commands to assign a different value based on external port condition. you will have to make sure the simulation can run successfully. Guangjun![]()
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RE: Input Capacitance Characterization in Cadence Liberate
Apart from introducing harness blocks, is there a way we can interfere into the "capacitance measurements" of a pin in liberate ? Instead of a fixed single value, to define a range of capacitances depending on i.e. an external condition ? So that in generated .lib file (shown below) : pin (A) { direction : input; related_ground_pin : VSS; related_power_pin : VDD; max_transition : 0.56; capacitance : 0.0289202; rise_capacitance : 0.0289202; rise_capacitance_range (0.000516565, 0.0289202); fall_capacitance : 0.0287069; fall_capacitance_range (0.000516728, 0.0287069); I want to say that pin A capacitance value (0.0289 - in this case quite higher since no input buffering), should be depending on output load. In other words, use the right input capacitance for input A (from rise_capacitance_range) depending on the output load. To the best of my knowledge, rise/fall capacitance range of this type of cell highly depends on output conditions. Anuradha![]()
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RE: Input Capacitance Characterization in Cadence Liberate
I am not sure that I understand your question(s) now. If you can characterise the arcs successfully, a harness will be the best way to account for non-linear capacitance contributed by external component---This has never be clarified by you. It is not clear to me what you meant or wanted with the last example. The default syntax with liberate-generated library is like the example. If you want to post-processing some attributes/values, you can use the user_data flow (please refer to write_userdata_library and search for other user_data, if needed). Or, you may try set_attribute command. Guangjun![]()
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Quantus: warning regarding separate field solver techfile with MEOL stack description
Hi! I am getting the following warning when performing Quantus extractions with the FS extraction mode: WARNING (NEBULAM-135092): Design is using device stack extraction in 'TSMC finfet' node. Foundry is supposed to provide separate field solver techfile with MEOL stack description. With current techfile you are not going to get sign-off certified accuracy for nets connected to MEOL devices. If you do have FS technology file and still see this warning request Cadence support to recover accuracy. Do I need to have some additional decks installed in order to use the FS extraction mode? I am using Quantus 18.2.1-s210 on TSMC 16FF+ PDK. Thanks and regards, Jorge.![]()
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