Once defined, I have found these liens in the .OPJ-file so just open one of them in a text editor and copy-paste.![]()
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RE: How to create a template for a BOM in OrCAD Capture 17.2
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RE: How do we prevent black box 3D models for footprints?
If component hight is needed and there are no Step models available, package_hight property can be defined for the PLACE_BOUND sub class. There can be several shapes on this class each with their individual height defined. Useful if no Step model is available and some means of a 3D representation is required.![]()
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RE: How do we prevent black box 3D models for footprints?
I set PACKAGE_HEIGHT_MAX for the boundry shape to 0 mm, and it also seems to do the trick.![]()
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skill code to generate OA abstract from layout
Hi All, I need to generate abstract for a whole lib layout cell. it would be better if I can generate them using skill code. Does anyone know this kind of skill code available ? thanks a lot Nhumai![]()
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loss of components when open schematic on another PC
I used orcad 16.5 to design the schematic but when I copy the project to other computer ( orcad 16.5 too), I face to this problem. all the components in schematic are loss like the picture attach. I try it with other 2 PC, one is ok but one is have same problem. anyone face to this problem please help me.![]()
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is it possible to extract the subcircuit names/models and the associated pins from input.scs ?
Hi there, I have the netlist file input.scs , on top is spectre but may include hspice files. I need a script/utility/command to extract from the entire hierarchy all the subcircuit definitions and the associated pin names of for each subcircuit. The order of pin names should be the same as in netlist. I assume that somehow spectre is doing all this stuff internally, is there any possibility to dump this info in a flat text file to be parsed after that? Thank you, Marcel![]()
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Die inclusion on an existing schematic and netlist
I have designed a schematic on Orcad Capture with active and discrete components. From this design was generated a netlist which was used on PCB editor to develop the circuit layout. Now I need to change packaged IC components by its bare dies. However, I have been facing problems to add the die format inside the design which I already have. The first attempt was to create the die on APD, export a .dra file and include this file as a component footprint on Orcad Capture. After the netlist is generated and imported in the APD or SiP layout, I can't select the die pads to create the wire-bonding and bond fingers. I also tried to create the die on APD trough text-in wizard and then import the schematic netlist. In this case I can create the wire-bonding and bond fingers, however, the connections between the discrete components and dies are lost. I'm looking for any help in order to discover the right process to do this development. I couldn't find any Cadence application notes that explain this flow. I will appreciate any help provided. Thanks in advance.![]()
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RE: skill code to generate OA abstract from layout
Hi Nhumai You can refer to $CDSHOME/doc/sklayoutref/sklayoutref.pdf for SKILL cmds which can be used for abstract generation. Best regards Quek![]()
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All the Ps: the Photonics PDK Panel
At DesignCon at the end of January, there was a panel on photonics. The title was Photonics Coming of Age: The Emergence of PDKs . The panelists were: Moderator James Pond of Lumerical (CTO). Lumerical provides photonic simulation software (and more) and is a partner with Cadence for an integrated silicon photonics design flow Gilles Lamant of Cadence (leading our work in photonics). I'm not going to introduce Cadence. Mohamed Youssef of Mentor/Siemens (foundry enablement). Mentor, now part of Siemens, is a leader in physical verification, an important part of a silicon photonics flow with its odd geometry with lots of curves. Samir Choudhry of TowerJazz (design enablement) TowerJazz is a foundry. Ashkan Sayedi of HPE Labs (working on PDKs for photonics). HPI is HP Enterprise, computing for companies (as opposed to HP which retained the consumer stuff like PCs and printers). Rui Santos of SMART Photonics (principal engineer) SMART is a pure-play InP foundry. Introduction to Photonics Since not everyone in the audience was really up to speed on silicon photonics, James started with an introduction. Photonics, he said, is: everything to do with light and its manipulation. The first basic building block is a waveguide, that lets you guide light around the chip. This can be made from silicon and also from indium phosphide (InP). It can support multiple modes (polarization, frequency). Light doesn't like sharp corners, but you can guide it around a curve (5um in silicon) with very little loss. Once you have a waveguide, you can couple and split, a bit like optical plumbing. The active building blocks (waveguides are passive) allow the phase of the light to be controlled electrically, either with a PN junction right in the middle of the waveguide, or with thermal phase control using a heater. This allows electrical signals to be converted to optical signals. In the other direction, photodiodes are used to detect light, so turn optical back into electrical. This usually requires a germanium layer to be deposited on top of silicon. There are two ways of handling the light source. One is to do that off-chip (or on a separate die in the same package). Alternatively, with InP it can be done on-chip naturally, but with Si it is harder and generally involves attaching III-V material. For a more detailed introduction to photonics, see my post about the recent Cadence summit Diwali, the Hindu Festival of Lights...and Photonics, the Silicon Festival of Light and other earlier posts linked from there. For manufacture, there is a big tradeoff. Indium phosphide (InP) is a premium material, and gives you a nice integrated laser, which silicon cannot do. On the other hand, if you want 8" and 12" wafers with high volume manufacturing then starting from silicon is the best. There are experimental options with InP being integrated into Si. But, in for now: Si doesn’t have a laser. It is the waveguide router. The challenge, and the topic of the panel, is that to make something useful today, you need a PhD in photonics. Obviously that is not scalable, and for ever photonic expert there are a thousand mixed-signal designers. What needs to be done is to bake in a lot of the institutional knowledge and best practices into a PDK (process design kit) to make it scalable, and enable at least basic photonics to be done by the non-initiated. Panel Discussion Question: What are the fundamental differences between electronics and photonics that will shows up in PDK differences? Gilles (Cadence): there are a lot of common building blocks such as simulation models, both electrical and optical. Both have schematic symbols. Layout generators. All mixed-signal designers know this stuff. One big difference is how layout is drawn, it's all curvy. That is the most visible difference, but there are also a lot of differences due to the fact that signals span a wide range of frequencies (light, electrical, thermal) and cover mulitple modes (electric, magnetic). This brings complexity to the PDK (and the tools). We try to hide it and make the waveguide look like wire, but behind the curtain, it is very different—a waveguide is a device with a model, not just a few Rs and Cs.. Mohamed (Mentor): electronic PDKs have been around for ages, but are not good at handling variations such as when resistors can go on different layers. then you end up with 300 components. On the photonics side there are fewer variations (no layer variations, no voltages). Electronics is very mature and every device is well parameterized by the foundry and simulated over a range of instances. But on the photonics side, some foundries are still providing black boxes, not parameterized across the full spectrum of parameter values. Physical verification is still needed for photonics, even for curved objects. Question: What about custom devices that are not in the PDK? Is that just that PDKs are immature? Do we foresee a day when all the devices are in the PDK? Gilles (Cadence): the components that you see in a photonics PDK are not R, C, Xtor level, but rather couplers, modulators etc and so the foundry can't always have exactly what you want. It's as if the foundries gave you a standard op amp, when there would always be something that you'd want to tune. Most of the optical components are at that level of complexity. What foundries can do is give a set of examples, but you're neve rgoing to find everything you need without any tuning. Ashkan (HPE): for electrical, specs and demands get generated in industry, foundry hears that, and they tune the process and the PDK. People who use the electronic PDKs don't know the deep physics—you just use the parameters that are exposed to you. In some ways, the difference between electronics and photonics is just a matter of wavelength. For a transmission line in electronics, which goes a long distance, you know automatically to widen the copper. Analogous things exist in photonics. Gilles (Cadence): With Spectre-AMS and Lumerical INTERCONNECT, we can not only do mix-signal but also mix-discipline co-simulation, and we can simulate systems including DSP core, SerDes analog, and optical, all together. Lumerical has used Verilog-DPI to tightly couple the optical simulator to the analog simulator (Spectre) including the true electrical loading of electro-optical devices on the electrical circuitry. So I would not say co-simulation does not exist. Samir (TowerJazz): when I started to do it myself, I got stuff and ended up putting together a reference flow which was very useful to our customers. Question: What about test and verification? Rui (Smart): Verification was a big challenge too, with equation-based DRC. On the electronics side, there are very few DRCs, and a waiver list which has been pre-negotiated. Tapeout is done in 24 hours. But photonics get 40,000 DRCs. You cannot submit GDS files with 40K DRC errors. The big need for a PDK is that a lot of guys would just draw shapes in Matlab and not use components that are correct by construction. Ashkan (HPE): Doing my PhD I was in the cleanroom looking thoruh an electron microscope building it myself. But that’s not going to scale. A lot in electronics reflects 50 years of institutional knowledge. At 7nm and 5nm, design rules are so limited, and we are not going to be there in the photonics world with curved structures. OPC is another whole can of worms for photonics too. Question: A lightning round, getting each person's 5-year forecast for photonics Gilles (Cadence): something more automated has to be done for things like a 50x50 switch array. Placement automation might never work, it doesn’t even work for analog, but maybe automation will work for routing. As to optimizing devices, very little has been done for robustness to process varation. There is lots of interesting stuff that could be extended to more structures than you see. Ashkan (HPE): In 5 years will see more photonics in the datacenter. What is on top-of-rack will come down. Pluggable at 5W is too much power, so it will go on the board. Design tools will mature. Foundries will be able to deliver known good wafers. There will be more schematic-driven co-simulation. We're at an inflection point right now. It’s the technology of the future all the time…but going from 12.5G to 25G datarates, customers demand it. We won’t be able to build electrical 200G SerDes. Photonics is needed to enable it. Samir (TowerJazz): James showed a graph of the market growing (see above). I hope it is growing faster. There will be standardization. We are the first open foundry (biosense, datacomm, lidar…). Designers will find a way to use “good enough” processes. Rui (Smart): We will see a jump in maturity during 5 year time. We will see price/cost down from prohibitive cost limited to telecom to devices for datacom, where InP come into its own. Sensing is where the big jump will happen. Customers populating airplanes with photonics sensing. Automotive. Volume markets. Mohammed (Mentor). One thing we’ll see in less than 5 years these little small research foundries will need to consolidate and mainstream foundries like TowerJazz and Smart and big foundrires will come in. I think we'll see maturity of PDKs in less than 5 years. And with that James thanked the panel released everyone for beer in the exhibit hall. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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RE: In layout window up and down arrows are not working for scrolling.. What may be the reason behind it?
Hi Bala You can check the current up/down bindkey cmds using: hiGetBindKey("Layout" "Up") hiGetBindKey("Layout" "Down") You can set them using: hiSetBindKey("Layout" "Up" "geScroll(nil \"n\" nil)") hiSetBindKey("Layout" "Down" "geScroll(nil \"s\" nil)") Best regards Quek![]()
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RE: recovery
Hi shokoufeh Virtuoso does not do any backup of your data. You will need to work with your IT department for data recovery. Most design centres use file servers which have some sort of automatic backup. Best regards Quek![]()
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RE: alignment of a pin on a component to a pin on an adjacent component
Thank so much Prasanth, I downloaded it and using it. Best regards, TiBo![]()
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In the 17.2 hotfix 051 environment, the buttons on the footprint viewer of OrCAD capture (zoom in, zoom out, zoom fit) do not work.
In the allegro17.2 hotfix 051 environment, the buttons on the footprint viewer of OrCAD capture ( zoom in, zoom out, zoom fit ) do not work.![]()
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RE: SpiceIn netlist->schematic
You have to use a device map to do the mapping. If you set the mapping up through the UI, you must save it (as far as I know) and then tell it to use the device mapping file on the first tab. I'm guessing you didn't do that, and so you've just got the default behaviour (i.e. no mapping). Perhaps you could clarify precisely how you set up the interface (maybe with some screenshots)? Regards, Andrew.![]()
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RE: is it possible to extract the subcircuit names/models and the associated pins from input.scs ?
Hi Marcel, Add an info analysis such as this into the netlist: subcktInf info what=subckts where=file (you can do this in ADE via the Outputs->Save All form). This will produce a file called input.info.subckts in the netlist directory (unless you specify a file to write it to) which includes the names of each subckt and the terminals (in order) for each subckt. Regards, Andrew.![]()
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RE: constraints file
During synthesis, you can sue some commands like: set_max_delay , to constraint the delay between your input and outputs. For STA, try using the command: report_timing -unconstrained![]()
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RE: loss of components when open schematic on another PC
First, make sure your installation has the latest service pack when graphics problems happen. Your symbols *should* be cached in your schematic DSN. This isn't 17.2, so I'd look at your settings. Does this happen with all schematics or just this one on other machines? Worst case, try deleting your Capture.ini config file (after making a copy of it) to see if an option was accidentally set. To reset your color preferences on a machine that does this, at the Design Manager tab, click Options> Preferences> Use Defaults> (down at the bottom)![]()
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Breakfast Buffet for January 2019
https://youtu.be/4N5bx3eR_9U The three highlighted posts for January were: Breakfast Nibbles: Predictions for 2019 AlphaZero: Four Hours to World Class from a Standing Start Persistent Memory Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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RE: Annotations are just way too overpowering
Sorry for the late reply - I've been away for a few days. I can't thank you enough for your help getting all of this up and running!! I've been able to take your suggestions and make an unobtrusive net voltage monitor, a bias leg monitor, and a cell that displays the cdsParams of another instance. I've attached a screenshot of part of one of my schematics showing those cells in action. The only thing I still wish for is being able to directly access the various simulation or model aspects without having to go through the awkwardly indirect route of cdsParam() i.e. it'd be great to directly access e.g. the gm of mp42 etc.![]()
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Take a lesson from the Amish...
“Time to design completion” is almost always the primary metric and the cause for the most angst within a design team. Your customers demand that a package design is completed as quickly as possible to minimize the impact to their overall schedule. Sometimes completing the task is not about difficulty, but about the volume of the work -- the number of interfaces, the number of routes, the placement of a large number of components. A single designer can be a bottleneck for no other reason than their design throughput. Sure, automation can significantly improve the capacity of a single designer, but sometimes the situation really needs multiple designers to collaborate, divide and share the load. Yes, you can build a barn with a single carpenter; you can obviously build it much faster with a team of carpenters. The Allegro PCB Symphony Team Design Option enables you to bring a team of designers and engineers to bear on a design to finish it faster, and it’s just not for PCB. Enabled as an option on the SIP Layout XL tier (either on the .mcm or .sip database) and available now, IC packaging design team members can share the load simultaneously between different designers and design disciplines on a common canvas; each contributor can see the updates being made real time. A large processor, RF, ASIC, or interposer design can have multiple designers working on different busses, functional areas or layers simultaneously, either under a formal distributed plan of attack using a design server, or on an ad hoc basis e.g. a layout designer consulting with a SI or PI expert as needed, simultaneously, on a specific challenging area of the design, in the same conference room or across the globe with just your own laptops with a minimum of set-up. Request a demo, and see how the Symphony Team Design Option can boost your team's throughput.![]()
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