In the QRC Techgen manual (extTechgen.pdf) it describes how stamped regions like well/substrate can be broken into regions around each substrate tap using stamp=2 in the layers_setup file. I think I have this working with Assura LVS and was wondering if this can also work with PVS LVS? The Techgen manual only describes what happens with Assura geomStamp regions. I gave this a try with the foundry PVS LVS deck but I think I need to create a modified deck to get it working. Thanks, Robin![]()
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QRC stamp=2 with PVS LVS
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"The First Half of 2019 Is Likely to Be Really Bad"
The title of this post was the single line summary of Dan Niles' quarterly outlook for the semiconductor industry. Dan is the founder and portfolio manager of AlphaOne NexGen Technology Fund. Each quarter GSA has a conference call with him where he presents what he is seeing. He starts from big picture stuff like unemployment and interest rates and works down to the outlook for the semiconductor industry. The title of his presentation this quarter was: Tariff Pull-Ins, Demand Fal-Off, and Excess Inventory—Not the Triple Crown You Want Note that everything below is what Dan said unless it is [in square brackets] when it is my additional commentary. General Economic Conditions In the second half of this post, I will go into more detail on what Dan said about the semiconductor industry and the end-markets that it serves. But here is the big picture in a few bullets (this is 35 slides condensed into half that many lines). "We believe that the US and Global economy slows but a recession is not likely in 2019. But we are not convinced that the S&P500 has seen lows for the correction." US unemployment near 50-year lows. Job losses near 50-year lows. US home inventories are at extremely low levels which is cushioning against mortgage rates being at 7-year highs. Commodity prices low and stable. Global leading indicators already rolling over (turning bearish) Central Banks helped create over $13T in sovereign debt, and $100B in corporate debt, with negative yields. Rates are now rising. This bond market bubble was created over 35 years and its deflation could be painful [bonds go up when interest rates go down, and we have had 35 years of declining interest rates...until now]. The graph below shows the US 10-year bond yield since 1962. Corporations have levered up at the wrong time (taking on debt, raising dividends, share buybacks). "We worry that corporate debt is the new subprime threat in 2019." Shiller PE (price/earnings) near 1929 levels (but they were higher still in 2000) Semiconductor Market One uncertainty is that tariffs pulled some demand from 2019 into 2018, which means there is excess inventory to be worked through. End-demand is below expectations with both smartphone and PC markets shrinking even before considering Apple's recent announcement about China. Semi sales were up 20% year on year in 2018 [driven a lot by memory pricing] but set to slow sharply. About 90% of semiconductor companies that have reported lowered their numbers [and TSMC reported after Dan's presentation and lowered theirs]. Poor end market unit growth versus strong semiconductor sales reconciling: PC demand now negative year-on-year for 7 years. Dan expected it to be up this year, but that didn't happen. Smartphones grew 28-58% in 2011-14 but down year-on-year for 2018 with ASPs and profit contraction likely in 2019. There is likely to be an additional trough due to the transition to 5G, but 5G not yet ready. Transition to self-driving cars drives huge semiconductor content gains, but not enough (yet) to offset PC/SP. 3B connected devices in 2013, 5B in 2015 with about 20% growth through 2020. 1 trillion cumulative IoT devices shipped by 2035 The inventory situation is not pretty: Apple inventories up 31% year-on-year, with TSMC and HonHai [FoxConn] up about 40%. Apple pre-announced negatively for the first time since 2002. PC OEMs not bad. Tight memory supply is now excess supply until mid-2019. Hynix inventory up 49%, Micron 20%. Communications inventory seems good. Automotive inventory is slightly elevated with poor demand. China automotive declined for the first time since records began in 1990 [and China is the biggest automotive market, bigger than the US, Japan, and Germany combined] Issues in smartphones and memory will have a large impact on semiconductor companies: Smartphone units are now shrinking along with PCs and combined are 35% of demand. China is 15% of global GDP but 25% of semi consumption with 25% of demand for PCs and handsets, 30% of auto, 20% of infrastructure. The overall economic situation in China is uncertain. Things will get really ugly in Q1, especially after Chinese New Year [February 5th]. Excess in memory markets will have an outsized impact on total semi revenues and capex [equipment] spend. Capital expenditures in semiconductor have been high for the last couple of years, and that will show up in supply starting this year. Even though capex is being cut back now, that won't help until 2020 since the 2017/8 capital expenditure is showing up this year. Capex. That supply from a year ago shows up in supply. So even though cutting back hard now won’t help until 2020, you will get 2017/8 spending showing up in 2019. See graph below. Conclusion First, some uncertainties that we have to wait and see how they play out: 2017 capital expenditure was up 38%, and then up 10% again in 2018. That will cause oversupply problems of some sort in 2019. How much inventory is in Apple and its supply chain? It was already high before they pre-announced negatively early in January. Dan is now hearing of inventory digestion at the largest hyperscale vendors as their capex slows. Automotive is not a large memory end-market, but 10 big global OEMs [car companies] have built up inventory, which would not normally be a big problem except China units [cars] down 3% year-on-year for the first decline in 18 years of records Lead times started stretching at the start of 2017, which helped drive a buildup of inventory. Leadtimes declined in 2018, but then concern over tariffs in late 2018 led to further inventory buildup despite slowing demand. "Made in China 2025" and the backlash from the US (eg ZTE [and Huawei]) is a Sputnik moment for China. This is a big problem for the US semiconductor industry going forward, much like what Japan did to memory in the 1980s and Korea in the 1990s. The longest ever DRAM rally (8 quarters) ended in Q4 as the spot versus contract discount rose to a double-digit percentage. Though the global economy is in better shape due to recent Fed action and China stimulus, a correction is likely through mid-2019 for inventories to be worked through. Severity could be worse than currently anticipated, especially in the lull post-Chinese New Year. The overall conclusion is the title of this post: the first half of 2019 is likely to be really bad. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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RE: Step files in Orcad PCB Pro 16.6
The issue is same for me.. but i cant find a way to update the hotfix.. how to update it??![]()
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RE: For a given instance name, Update the sub-cell name in schematic
Hi Anuj, Well essentially you need two nested foreach loops - the outer loop iterating over the cells, the inner one iterating over the instances in each cell: (foreach cell '("c1" "c2" "c3" "c4" "c5") ....open cell view in terms of dbOpenCellViewByType (foreach inst '("i1" "i2" "3") ...do the replacement ) ) but...is it really always the instances i1, i2, i3 in all cells? Or is it all instances in each cell? And with respect to the swapping of an instance's master cell (that's what you mean with subcell right?) - are you deleting the old instance and placing a new one or do you want to remaster the existing instances (which is not a trivial task). And which subcell/master is supposed be replaced by which other subcell/master? Is there a mapping between old and new subcells. Sorry for not being able to give a more specific answer but your question itself is pretty general. So yes - I think some further explanation would be helpful.![]()
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How to run jitter tolerance analysis in cadence
Hi, I am designing clock and data circuit, I want to do jitter tolerance analysis in cadence, how to run the simulation? Is there any guide or reference to do jitter tolerance analysis in cadence virtuoso? I am using IC5 and IC6. Thank you.![]()
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Importing a PCB Label with text
I am looking to see if there is a way to import through the schematic a netlist pcb label. What I am looking to is is create a symbol in the schematic with a ref designator which represents the PCB part number that would be put in etch in the pcb. I know I can create a pcb symbol that has text in it that would be carried over in the netlist but I want to know is there a way to bring over the symbol with the pcb number for that actual board so I do not have to edit the text everytime in the pcb layout. Is there a way to put the pcb part number in a property of the schematic, like a resistor or capacitor value, which comes across in the netlist.![]()
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RE: OrCAD schematic capture - how best to break up a connector?
How is this really accomplished? If each pin a a separate symbol, how do the multiple symbols get mapped to one single connector?![]()
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ODB++ Export does not include Non-plated drills.
Hi forum. I think I must be missing something. When I try to export OBD++ files, the non-plated drill hits seem to be missing. I'm using 17.2-2016 S050 Here are my settings: page 1) Page 2) Page 3) Page 4) And the resulting artwork, the blue circles note where the NP drills should be. In my CAM tool, I've inspected the drill table, there is no tool code for the drill size I'm looking for. It's like the drill is being completely omitted. Any ideas would be helpful. Thanks.![]()
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RE: Dynamic Shapes not pouring correctly
In the second case, your Pin-to-shape spacing constraint is generating the second outline.![]()
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RE: Dynamic Shapes not pouring correctly
The clearances should have produced the orange curves and not add the green curve. This is the error! The green smoothing should not have been applied.![]()
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RE: For a given instance name, Update the sub-cell name in schematic
Thanks "mbracht" for looking into the test case. Please find the detailed response below: 1) In the cell, there are many instances, of which I only want to look for "i1, i2, i3" instances, if these are present or not. This is to be done individually for all cells. c1, c2, c3, c4, c5. 2) Yes, by sub-cell, I mean instance's master cell. 3) Regarding the swap : once we locate the presence of those instances in a cell, I want to replace the corresponding sub-cell with new sub-cell or we can say symbol which is present in same library as the old cell to be replaced. Yes, I have a mapping for the new subcell to be replaced with. But this is regardless of the old subcell (Since the old and new are part of same library and we just care of the instance name). So, basically, the need is to look for those 3 instances in a cell. If it is present, then replace that subcell or symbol with new one from same library. Hope I made myself clear. Kindly let me know the skill code solution to the same. Also, please share the proc to swap the subcell/symbol in schematic. Thanks, Anuj![]()
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Spectre Tech Tips: Optimizing Spectre APS Performance
As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre ® APS for analyzing your designs. Do you sometimes wonder if it were possible to optimize Spectre APS further for accuracy or performance? If yes, then this blog is for you. In this blog, you'll get to know how you can optimize Spectre APS performance for analog and mixed-signal designs using some important options. You'll also understand how you can address some typical setup problems that cause performance issues and how to use some of the advanced methods to optimize simulation performance. Pre-layout Simulation Accuracy/Performance Trade-Off For pre-layout simulation, you can use the following two options to adjust accuracy and performance: The errpreset option with values conservative , moderate , and liberal , defines the solver tolerances. While conservative is the most accurate, liberal provides the highest performance. The errpreset option can be specified in the netlist, or at the command line with +aps and ++aps (i.e. ++aps=moderate ) options. The ++aps command-line option provides performance optimization for each errpreset setting. It typically provides 1.5-2x performance gain over the same simulation with +aps , with no or minor degradation in accuracy. When running the simulation on a new analog/mixed-signal design, we recommended that you start with the ++aps=moderate setting and use the default values for all other solver options. If Spectre APS accuracy isn’t sufficient, you can improve the accuracy incrementally by moving to +aps=moderate , ++aps=conservative , and +aps=conservative till the required accuracy is achieved. If the ++aps=moderate run provides good accuracy, and you want more performance, move to +aps=liberal and ++aps=liberal to improve the performance incrementally while ensuring that the highest performance setting still provides sufficient accuracy. You can also set the errpreset and ++aps options in the High-Performance Simulation Options form in Virtuoso ® ADE, as shown below. Use the +mt command-line option to enable multithreading, which provides additional Spectre APS performance gains over a single-threaded simulation run ( -mt ). For small-to-medium sized designs, 4 core simulations ( +mt=4 ) provide the best performance, while for large and post-layout designs, 8 ( +mt=8 ) or 16 ( +mt=16 ) core simulations are recommended. By default, Spectre APS uses 8 cores (if available on the machine), however, it reduces the number of cores based on the design size. You can use the +query=mtinfo command-line option to identify the number of cores recommended for a given design without running the actual simulation. This information is provided in the Pre-Simulation Summary section of the Spectre log file, as shown below. ~~~~~~~~~~~~~~~~~~~~~~ Pre-Simulation Summary ~~~~~~~~~~~~~~~~~~~~~~ - (APS) Multi-threading. The recommended number of threads is 16, consider adding +mt=16 on command line. ~~~~~~~~~~~~~~~~~~~~~~ The number of threads can also be defined in the High-Performance Simulation Options form in Virtuoso ADE. The Auto selection uses the default Spectre multithreading behavior. When running a multithreaded simulation on a compute farm, set #Threads to lsf to allow LSF to allocate the cores. Spectre reports the number of threads used in the log file with the following message. Multithreading Enabled: 16 threads in the system with 36 available processors. Post-layout Simulation Accuracy/Performance Trade-Off While errpreset , ++aps , and multithreading also apply to post-layout designs, using the +postlayout option is the key for achieving good Spectre APS post-layout simulation performance. The +postlayout option enables optimized simulation technology to calculate the DC operating point for large designs, performs RC reduction including coupling cap handling, and deploys enhanced matrix solving for RC-dominated designs. For most analog/mixed signal designs, the +postlayout=hpa (high precision analog) setting provides the best performance and accuracy trade-off because it uses conservative RC reduction. For very sensitive designs and extreme accuracy measurements, you can use the +postlayout=upa (ultra precision analog) setting, which disables RC reduction, however, it still takes advantage of all other Spectre APS post-layout technologies. For high performance requirements in functional verification, +postlayout may be used, which uses more aggressive RC reduction. The post-layout settings can also be defined in the High-Performance Simulation Options form in the Virtuoso ADE. The +postlayout setting is called Default in Virtuoso ADE. When RC reduction is enabled with +postlayout or +postlayout=hpa , the reduction rate is reported in the Spectre log file, as shown below. Parasitics Reduction Enabled. (Resistors reduced by 80.53% Capacitors reduced by 88.36%, 71.97% of capacitors are coupling after RC reduction). High Voltage Applications High voltage applications are challenging for circuit simulation because with relref=sigglobal in moderate and liberal mode, vo lt age references are used globally over all signals. A maximum voltage of 10V from a high-voltage domain may impact the simulation accuracy of the neighboring 1V voltage domain. This problem may also be visible in non-high voltage applications where Verilog-A blocks create large voltage/current values artificially, or in designs with dangling nodes carrying large voltages. The related scenarios can be identified by checking the maximum value quantities in the Spectre log file: Maximum value achieved for any signal of each quantity: V: V(I4.net01) = 25.93 V I: I(V1:p) = 103 mA ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Post-Transient Simulation Summary ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - The circuit contains signals of the voltage > 10V, consider to set highvoltage=yes to get better accuracy and convergence ability. If a high voltage scenario is identified, it is recommended to use the highvoltage=yes option. This option introduces voltage binning for different voltage domains ( bin_relref=yes ), excludes Verilog-A terminals from convergence checking (default since Spectre 17.1 ISR10), excludes dangling node voltages from quantity checking (default since Spectre 17.1 ISR4), and overcomes the high-voltage related challenges. The highvoltage option can also be set in the Main tab of the Simulator Options form, as shown below. Typical Spectre APS Setup Issues While debugging customer cases for performance and accuracy issues, we’ve noticed that many such problems are due to an incorrect Spectre APS set up. These problems significantly slow down the simulation or degrade simulation accuracy. They can be addressed easily by understanding their impact on the simulation and taking the corrective action. Some of the problems and their solutions are listed below. Simulator settings from previous simulations not being appropriate for the current design Too tight reltol settings (for example, reltol=1e-5 ) cause many Spectre APS performance issues. Since Spectre APS is optimized for accuracy, using the default value for reltol is sufficient for most designs. Unreasonable values used for gmin and cmin may cause Spectre APS accuracy issues, which can be addressed by setting their values to default. It is recommended to use the default values for reltol , vabstol , iabstol , method , gmin , and cmin . If tuning is needed, then for most cases, it should be sufficient to change errpreset and +aps / ++aps . The following figure shows the default Spectre tolerance values in Virtuoso ADE. Note that there may be high-precision designs, or simulation/measurement requirements, that need custom tolerances. In addition, you might encounter convergence challenges for which you require special gmin / cmin settings. It is fine to tune these settings if you are not able to achieve what you need with the recommended errpreset settings with default tolerances. Simulating post-layout designs without setting the +postlayout option Many users assume that Spectre APS does post-layout optimization and RC reduction by default. However, Spectre APS, by default, does not enable any post-layout optimization/reduction, and may therefore be extremely slow on RC dominated post-layout designs. Check the Post-layout Simulation Accuracy/Performance Trade-Off section for proper post-layout settings. Too many node voltages, device, or subckt terminal currents saved Saving large numbers of waveforms, especially current waveforms, degrades Spectre APS performance significantly. Therefore, you should save only the waveforms you need and avoid saving everything ( save=all , currents=all , subcktprovelvl=10 ), if not required. The Spectre log file provides information about how many waveforms are created and prints a warning if performance degradation is expected. Output and IC/nodeset summary: save 355350(current) save 130338(voltage) WARNING (SPECTRE-294): Too many saved signals. Slow initialization is expected! Features not needed being enabled Spectre provides some powerful features, such as asserts for device voltage and current checking, info for design information printing, and design checks for analyzing design problems like high impedance nodes or leakage paths. These features, although important, degrade Spectre APS performance. Therefore, if you do not require these features you should disable them for maximum performance gain. The enabled features are listed in the Spectre log file, as shown below. Analysis and control statement inventory: info 6 Design checks inventory: dyn_highz 3 dyn_dcpath 1 static_voltdomain 1 assert 2139 Maxstep limiting simulation time steps Sometimes, maxstep is used to increase simulation accuracy or to improve periodic measurement (i.e. FFT) precision. It is recommended to use errpreset to tune the simulation accuracy. If you want to enforce time steps at periodic measurement points, use strobeperiod instead of maxstep . Extremely small rise and fall times Extremely small rise and fall times in Spectre source elements, or in Verilog-A modules, may cause Spectre time step rejections and significantly degrade Spectre APS performance. Therefore, it is recommended to use similar rise and fall times, as the circuit being simulated. Verilog-A behavioral modelling issues While Verilog-A behavioral modelling provides great flexibility for writing behavioral models, it may significantly degrade Spectre APS simulation performance, if written inappropriately. Typical problems include initial calculations being performed at each time step, transition statements like cross / above / boundstep limiting and rejecting time steps, transition filter functions missing, and using resistance instead of conductance equations. Therefore, it is highly recommended to run the Spectre AHDL linter ( -ahdllint=warn ) utility on any newly-written Verilog-A model, and address any reported modelling issue. The AHDL linter utility can also be enabled in the Miscellaneous tab of the Simulator Options form in Virtuoso ADE, as shown below. Using an older version of Spectre With every release, Spectre APS is enhanced for better performance. As a result, when you use an older version of Spectre, you miss out the performance enhancements that have been made in the latest version. Therefore, we recommend that you use the latest Spectre release for your designs. Hardware issues Spectre APS performance is impacted when a machine is heavily overloaded, if there are network performance issues, or if sufficient memory isn't available. Insufficient memory can lead to swapping and slow down the simulation. You can check the available memory in the header of the Spectre log file. Machine loading and network communication problems can be observed by checking the CPU load or the utilization reported in the Spectre log file. A CPU load close to 100% could point to a heavily overloaded machine. A utilization below 90% for a single core simulation, below 150% for a 4 core job, or a utilization below 300% for a 8 core simulation may point to an overloaded machine, or network problems. User: stefanw Host: lnx-stefanw HostID: CD0A11B8 PID: 11716 Memory available: 10.1099 GB physical: 16.6440 GB During simulation, the CPU load for active processors is : Spectre 0 (99.9 %) 1 (99.7 %) 2 (99.7 %) 3 (99.7 %) 4 (99.7 %) 5 (99.7 %) Time used: CPU = 10.8 ks (2h 59m 57s), elapsed = 18 ks (4h 59m 49s), util. = 60%. Tips for Further Performance Improvements Following are some tips that will enable you to enhance the performance of Spectre APS further after you have already followed the steps on how to resolve any setup issue. Using performance optimized DC For designs that take a long time in calculating the operating point, use the +dcopt command-line option which provides a performance-optimized DC calculation. The option may cause minor degradation in the accuracy of the DC solution and is therefore not a solution for designs that are highly sensitive to an accurate DC solution. The +dcopt option can also be set in the Environment Options form in Virtuoso ADE, as shown below. Changing simulation settings dynamically The dynamic parameter feature enables you to define different solver settings for different time windows. If your design has different accuracy requirements for different time windows, you can use the dynamic parameters to speed up the overall simulation. Dynamic parameters can be defined by selecting transient analysis ( tran ) in the Choosing Analyses form in Virtuoso ADE, as shown below. Using the save/recover simulation state If multiple simulations have the same start-up sequence, you can use the savetime and recover options to run the start-up sequence once, save the simulation state at the end of the start-up sequence, and then restart all other simulations based on the saved state. The savetime value or the recover file can be set in the State File tab of the Transient Options form in Virtuoso ADE, as shown below. Using Spectre XPS MS If some portions of the design are digital, and you can afford some accuracy degradation on the digital blocks, you can improve the simulation performance by using Spectre XPS MS. Spectre XPS MS shares the use model with Spectre APS and enhances the performance by using the Spectre XPS FastSPICE tool for the digital portion of the design. The accuracy of the analog portion is still maintained by using the Spectre APS engine. Spectre XPS MS requires the power supplies of the digital blocks to be ideal voltage sources, otherwise, digital detection will require setting up voltage generator nodes and voltages. Spectre XPS MS can also be enabled in the High-Performance Simulation Options form in Virtuoso ADE, as shown below. Debugging Spectre APS Performance Issues By utilizing the tips given above, you can address a majority of your Spectre APS performance issues. In addition, Spectre APS provides a simulation diagnostic mode, which can be enabled by using the +diagnose command-line option, or the +diagnose=detailed netlist option. The diagnostic mode analyzes the simulation statistics over the transient simulation time and reports detailed information on which signals/devices/elements cause convergence problems, time step reductions/rejections, and slow down simulation performance. The diagnostics mode can also be enabled in the Check tab of the Simulator Options form in Virtuoso ADE, as shown below. If you run into Spectre APS performance issues, which you cannot resolve, it is recommended that you run the simulation using the +diagnose command-line option and discuss the diagnostics report with your Cadence support AE. Related Resources Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide Virtuoso ADE Explorer User Guide Getting the Most Out Of Spectre APS You may also contact your Cadence support AE for guidance. For more information on Cadence products and services, visit www.cadence.com . About Spectre Tech Tips Spectre Tech Tips is a blog series aimed at exploring the capabilities and potential of Spectre®. In addition to providing insight into the useful features and enhancements in Spectre, this series broadcasts the voice of different bloggers and experts, who share their knowledge and experience on all things related to Spectre. Enter your email address in the Subscriptions box at the top of the page and click SUBSCRIBE NOW to receive notifications about our latest Spectre Tech Tips posts.![]()
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RE: Capture tcl script to add/modify properties on all parts
I know this is old, but I just found you can get the current page with: set activePage [GetActivePage]![]()
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RE: Copying p-cell from one library to another.
Hi Ganesh, The right thing to do here is to contact customer support (as I suggested earlier). Doing this without visibility of either your data or the PDK makes debugging this virtually impossible - I'm having to guess each time what the behaviour might be. Regards, Andrew.![]()
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Quantus QRC (PVS interface) error
Hello, I am not sure if this is the right forum to post issues regarding Quantus QRC. If it isn't kindly, move the thread to the appropriate forum. I was trying to use Voltus FI for EMIR analysis. The rak is titled "Voltus-Fi-L EMIR Analysis Workshop". The basic flow has you do LVS with PVS followed by extraction using Quantus QRC's PVS interface. This is then used as an input to Voltus FI. The LVS ran without any issues but I get the following errors during RC extraction. ERROR (CAPGEN-41313): The options "-delta_gate_ckt" OR "-delta_gate_ckt_by_device" OR "res_gate_factor/res_gate_default_factor" can't be used together "exclude_gate_res". Restate input options. ERROR (RCXSPIC-27225): /public/cadence/618/EXT182/tools/extraction/bin/64bit//capgen failed with status 25 For what it's worth I am using EXT18.2 version, not the 18.1 version. The drop down menu in the layout editor now says Quantus instead of QRC like it does in the rak.![]()
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RE: Quantus QRC (PVS interface) error
Hi mhkvy4 You have posted to the right forum. Would you please try the following? a. In Quantus form, go to "Extraction" tab b. There is most probably a default value of "2" in "Gate Resistance Factor" field c. Please remove it and retry extraction Best regards Quek![]()
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RE: QRC stamp=2 with PVS LVS
Hi Robin Stamping in layer_setup file works for both Assura-QTS and PVS-QTS flows. Would you please provide more details on the modifications which you had done for the PVS LVS deck? Best regards Quek![]()
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RE: Passing parameters into an ocean script...
Thanks Andrew. Your example just made me think of something. I'm at home so I can't try this out, but rather than having 3 separate "header" scripts and a common code script, why couldn't I just write *everything* as a single procedure. All I'd have to do is load it first and then I could just invoke the procedure and pass all the parameters I want that way. It is a two step process (for the first run only), but it's only one file to worry about...![]()
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RE: Quantus QRC (PVS interface) error
Yes, that made it work. Could you explain what the default value of 2 implies? I am assuming leaving it blank means gate resistance is not taken into account when doing RC extraction. Thanks.![]()
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RE: Passing parameters into an ocean script...
Yes, that would work, of course. Andrew.![]()
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