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not_gate verilogA model in ahdlLib
The following lines are in the verilogA model of "not_gate" in ahdlLib. I have marked 3 lines as A, B, C. @ ( initial_step ) begin ... > end logic_in = V(vin) > vtrans; // line A @ (cross(V(vin)...
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filter_sg in dyn_floatdcpath check
Hello All, I was exploring dyn_floatdcpath check in spectre. Came across a filter , filter_sg. But couldn't make it work at all. Any suggestions on how to use this filter?
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RE: not_gate verilogA model in ahdlLib
Nagendra, One benefit is that this wouldn't have hidden states for SpectreRF because logic_in is updated on every timestep. Without line A, it would only get recorded on the crossings - so there would...
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RE: not_gate verilogA model in ahdlLib
Thanks. Out of curiosity, will pss with initial transient(tstab) look at what is inside @(initial_step) begin ... end?
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RE: not_gate verilogA model in ahdlLib
Yes, it should do. Note, I didn't actually test this model with pss - this is from visual inspection only... Regards, Andrew.
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Parametric Analysis - Random Values
Hi Friends, In the ADE L - parametric analysis, I could see options to sweep the variable in the linear/logarithmic/auto etc between the specified min and max values. But is there any option to provide...
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RE: filter_sg in dyn_floatdcpath check
This is an unpublished parameter of dyn_floatdcpath, so it's not documented. That said, it seems to be used fairly often given the number of references to it in CCRs. You should contact customer...
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RE: Parametric Analysis - Random Values
Thank you very much Andrew for your quick reply. I will try Monte Carlo analysis Regards, Vijay
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Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP
What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers...
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RE: residual cdf parameters after switching lib
Hi David I am not sure if this can resolve your problem, hope that it will be helpful: procedure( CCSremoveParams(newLib) let( (cv cdfTable techLib baseCdf instCdf paramList)...
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RE: How to remove unused parts from an Allegro 16.6 PCB file
I don't normally post-process designs the way you are doing so I'm not sure why the part is hanging if it's been deleted. However, you can do a PURGE from the EDIT->PADSTACKS menu item and choose...
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RE: Reuse of Allegro PCB board file with new schematic in Design Entry
Yes. The schematic will need to match the layout. The only requirement is that the symbol pin numbers connect to the same points. Net names are not important. However, you can Export->Netlist and...
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need help in processing a list
Hi, I have a list of repetitive elements & non-repetitive elements in it. I need to process this list so that new list has elements only one time eg : A= list ( 1 2 2 3 3 3 4 4 4 4) the processed...
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RE: need help in processing a list
Hi Raghu, There are quite a few existing posts which cover this, including profiling of various approaches (may not be important unless your lists can be very long). Read the threads not just the...
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Take Advantage of Advancements in Real Number Modeling and Simulation
Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly...
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RE: Capture cloud?
So to be able to download Arrow Capture Cloud schematics for the desktop costs an extra $99/yr ? There seem to be two different "clouds" at this point too... there's the one through ultra-librarian and...
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Autonomous Cars, Vision, and Protocols
Remember how, last May, I wrote about the five levels of autonomy of the autonomous car? I’ve been thinking about cars a lot because I just got a new-to-me car, a 2015 model (I won’t tell you what it...
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Inconsistent "PSD" results between MATLAB & Cadence Calculator
Hi all, I have been trying to verify the variance (total power) of a random normal distributed noise source. The noise source model has been modified from the noise_src in ahdlLib but with...
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RE: Reg : snap to edged using a keyboard key
Hi Andrew, Thank you for the solution. It is working very good. Thanks, Ganesh Doddipatla.
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