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RE: Drill_Fab Artwork \ Gerber is Blank
The undefined line width setting is based on a film name by film name so select the drill artwork film name and make sure the undefined line width setting is actually set to something more than zero.
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Is Big Brother Watching You?
I recently came across a fascinating piece by Paramal Satyal . He is Nepalese although these days he seems to live in France. His piece is largely autobiographical, but what caught my eye was a bit in...
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NCELAB WOUPSR errors
I have a UVM testbench which gives the following errors when I compile: $cast(arg, tr); // Need run-time casting because at compile time T1 can be scalar. | ncelab: *E,WOUPSR...
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How to follow a wire in the layout?
I have a mixed-mode layout designed by someone else and want to track the digital clock routing path in the Layout GXL (metal layer changes in the path). I open the layout VIA the schematic window but...
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RE: NCELAB WOUPSR errors
Unfortunately this is as much information as you can get for that exact error (I feel your pain, I've hit it a few times myself). The problem is caused by a multi-language TLM extension that is in the...
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save the highlighted net to another layout
Hi all I want to save the highlighted net to a new layout view. I found that leHiSaveAllHighLightMarkNet() can save the marked net to a new layout view, but it only saves the metals and poly, it does...
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RE: NCELAB WOUPSR errors
Ok, I found it and changed to a packed struct which fixed the problem. Thanks for your help.
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Wind of Change in Hardware Design
After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I stepped out of the office yesterday. While I’m sure it will be cold again by the time this blog gets published,...
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RE: save the highlighted net to another layout
While you are in markNet mode, press F3 and enable retain via information for saving.
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residual cdf parameters after switching lib
hi exports, I have a question about cadence. say we have two sets of libraries. libA has full set parameters for the cells while libB has less parameters for the same cells. once the design switched...
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Science Fiction and Technology Reality
Stories have to be told or they die, and when they die, we can't remember who we are or why we're here. —Sue Monk Kidd, author I just had an awesome weekend with my sister visiting San Francisco from...
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VCD FIle Input to ADE-L
I'm trying to use a .vcd file as an input to my ADE-L and using Spectre as a simulator. I opened Setup -> Simulation Files and put the .vcd file in the path. Questions: 1.) Will Spectre work as a...
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RE: Drill_Fab Artwork \ Gerber is Blank
Hi Steve. Tried by giving 0.2mm for undefined line width and 2.54 for shape bonding box. Still only getting the outline in artwork. Have attached the screen shot for reference.
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RE: How to follow a wire in the layout?
Maybe the layout wasn't created with Layout XL/GXL and so doesn't have connectivity information? Perhaps you need to do Connectivity->Update Components and nets? Otherwise you could use...
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RE: Creating a Board outline
There are a number of methods you can use. Are you using Allegro PCB Editor or Orcad Layout? We use AutoCAD to create the board outline. Then we save as a Revison 12 DXF. and use the DXF import to...
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RE: VCD FIle Input to ADE-L
Al, Yes, you can use spectre. This is documented in the Spectre® Circuit Simulator and Accelerated Parallel Simulator User Guide in the Verilog Value Change Dump Stimuli appendix (appendix E in the...
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RE: bindkey to toggle between leHiMarkNet() and leHiUnmarkNet()
The code works for me, although it probably makes more sense to be: procedure(CCFtoggleMarkNet() if(hiGetCurrentWindow()~>markedNets then hiGetCurrentWindow()~>markedNets = nil printf("MARK NET...
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Paul Kocher: Differential Power Analysis and Spectre
Paul Kocher is a legend in security. A couple of weeks ago SiFive hosted a seminar by Paul. They do these regularly, usually on a small scale, but this one required a large conference room in the San...
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RE: Innovus: Does not detect Inverters in library
FYI, The problem is with having multiple power rails. The cells have VDD and VSS plus two other rails, which is specified in the liberty multi-rail format v2. Reverting to liberty multi-rail format v1...
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RE: Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS...
Hi Andrew, Yes, I works now. Thank you. Best, Christon
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