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Application Engineers Are Like Gold
I wrote recently about my experiences Running a Salesforce , and one of the key aspects of marketing in City Slickers Marketing . Today, it is time for my thoughts on application engineering....
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Cadence Innovus: Corner pads placed with no offset
Hi, I am using the MMMC-flow of Cadence Innovus. Hereby, I set the IO placement file and then initialize the design using the command init_design. My IO file looks like the following: Code: (globals...
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SDF back annotation after synthesis fails: No timing checks annotated
Hi, I am trying to perform a post-synthesis simulation. For synthesis, I am using Cadence RTL Compiler 14.2and my target technology is UMC 65nm. To perform the simulation, I write out the SDF file...
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RE: Transimpedance Amplifier - Broadband Circuit - Cadence Noise Summary
By "in Cadence" I assume you mean using Spectre in the Analog Design Environment - there is no tool called Cadence (that's the name of the company, not the software). If you're using a different...
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A Walk Through DesignCon Turns Into a Long Journey
Have you ever attended the DesignCon show? I attended the recent event for the first time and was surprised by what I saw: tons of high-bandwidth coax cables, circuit boards, connectors, and other...
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What I Learned about System Design Enablement at DesignCon
While attending the recent DesignCon show for the first time, I was struck by the many displays of cables, connectors, boards, and various kinds of test equipment (you can read about the impact this...
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Spacing between shapes
Hi all I'm drawing the power plan. I have a big shape (principal). Inside a this shape I need to draw other shapes more small. For evry shape i want to have different spacing. (shape to shape)....
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controlling mismatch & other related queries.
Hello, I have few queries related to mismatch- 1. In my understanding if we select 'mismatch' in MC simulation, it means comparing electrical parameters between identical devices on a single wafer. It...
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RE: Constraint info
Hi Paul Usage of constraints is quite simple. We just need to know the following key points: - There are 3 classes of constraints (electrical, placement and routing). You are most probably more...
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RE: skill command for layout execution
Hi Supriyo Would you please help to do the following and provide the output of the cmds? a. Select the 4 instances in your layout b. Execute the following cmds in CIW: geGetSelSet()~>name...
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RE: skill command for layout execution
Hi Quek, Please see the attachment. The image is slightly poor in quality since had to meet recommended size limit. Regards Supriyo
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RE: skill command for layout execution
Hi Supriyo Let me reproduce the info here: name: T5(1) : net06, net06, VDD T5(2) : net06, net06, VDD T4(1) : net06, net012, VDD T4(2) : net06, net012, VDD Your are using IC616-500-1. Would you also...
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RE: skill command for layout execution
Please see the result a) > geGetSelSet()~>instTerms~>name (("g" "d" "s") ("g" "d" "s") ("g" "d" "s") ("g" "d" "s") ) > b) getVersion( 'subVer ) "sub-version IC6.1.7-64b.500.14 " >...
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RE: skill command for layout execution
Hi Supriyo Would you please try the following? a. Please use IC617-500-14 instead of IC616-500-1? Your version of IC616 is too outdated b. There does seem to be a problem with the custom pattern. Even...
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RE: skill command for layout execution
Thanks Quek. It seems like the workaround does not work for IC617. Please see the screenshot. However, with what we have figured out so far, I do have a workaround in IC616. Also I have become a bit...
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Require Help regarding adding custom layer/extraction in GPDK45nm
Hi All, I am using gpdk 45nm & require some help regarding adding custom OXIDE layer in Virtuoso layer (say COXIDE). I am able to add custom layer in the layer pallete and draw it. But i have the...
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RE: Cadence Innovus: Corner pads placed with no offset
Hi, I fixed this issue by adding a (endspace gap = xx) entry after the last functional pad (I somehow misread the documentation on this in the first place). This works :) Is this the right approach?...
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PCB Design for Noobs
Hello, I have an original circuit that I've been soldering up on perfboard with a ton of jumper wires and am getting sick of it taking all day to build 'em. I'd like to transfer the schematic over to a...
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Virtuoso XL LE: Extract connectivity through "empty" areas
In layout XL, there are layers defined that are electrically connected. However, in most technology, the substrate is just empty area. So is there a way to set up the techno so this empty areas are...
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RE: Unable to map design without a suitable latch. [MAP-3] [synthesize]
a aspect evaluation to see exactly what number of questions in assignment writing uk they had been asking and how many constructs they were trying out . It’s frightening that there may be a...
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