RE: Time log
That's where it was hiding. Thanks so very much. I thought I needed to setup an NTP time service option and point it to a Sever in the File Properties dialog box. I just could not get that to work.......
View ArticleRE: Time log
That's where it was hiding. Thanks so very much. I thought I needed to setup an NTP time service option and point it to a Sever in the File Properties dialog box. I just could not get that to work.......
View ArticleRE: Orcad Capture - Slow Graphics response on windows 10
Hi Michal. I did indeed update but no luck, 2d performance in capture on win 10 is seriously slow. As of January 4th my windows 10 build is at 1709 (Build 16299.192) - fully up to date. The basic same...
View ArticleRE: How to short a net and a shape on layout using VIA
Hi On your schematic you have three nets, VSS, AGND, PGND. Are you wanting to short VSS and AGND to the PGND Shape with vias on the board using the net_short property. Perhaps I am reading this wrong...
View ArticleRE: How to short a net and a shape on layout using VIA
Hello Paul, The final goal is to short VSS and AGND to PGND. However, in the picture both VIA are connected to AGND. I would expect that once net_short has been set on both they should be connected...
View ArticleQueue list in job policies of ADE
Hello All, Under the job setup in ADE, there is a drop down under "queues" where I can select the available LSF queues. Earlier I was able to see "normal , regress, hwsim" . Now only normal is showing...
View ArticleRE: How to short a net and a shape on layout using VIA
Quite hard to tell exactly what is going on from just a screenshot but possible issues could be: Shapes are Dynamic and not up to date, check Shape>Global Dynamic Parameters or Design Status; the...
View ArticleRE: Inter Layer Checks - Same Subclass to Subclass?
I don't think it's possible unless you have access to Ravel and you can write a custom DRC. You may also be able to do this with skill. Good reason to be able to do it though so file and enhancement...
View ArticleNumber of accepted tran steps in spectre log
When a transient analysis in spectre is done, in the log file there is a statement " Number of accepted tran steps" . And it shows a big number. However in the statements above, a very few number of...
View ArticleRE: How to short a net and a shape on layout using VIA
Hi oldmouldy and thanks for your reply. PGND shape is dynamic. Indeed you can see that the vias are completely surrounded by it (because of the NET_SHORT property on the VIA)rather than having the...
View ArticlePSS issue when enabling APS multicore simulation
Dears, I'm currently facing the following problem: When running PSS simulation using Spectre or APS (Multithreading Disabled), stabilization time simulation (and subsequent PSS iterations) runs through...
View ArticleCES Keynotes: Cars, Flying Cars, Dancers, Music, Lights...and Sustainability
As I said yesterday , it was the Consumer Electronics Show this week. I attended the two big keynotes. The opening keynote on Monday night is traditionally Brian Krzanich of Intel. The next morning,...
View ArticleRE: Allegro Replicate
Replication method not useful here, like for me. You have to invent your own way of project. At legit website of Allegro you can read documentation.
View ArticleRE: Allegro Replicate
Hello, Yes, this is the way it works. All clines, shapes and vias, which are electrically connected to the circuit, are automatically selected during Place Replicate creation even if the layer is not...
View Articlevariable $freq in veriloga
Can use $freq in veriloga if I want to create an expression for say a frequency dependent gain in AC analysis? I gave this a try but so far it hasn't worked but the veriloga compiler and the spectre...
View ArticleRE: variable $freq in veriloga
Robin, There's limited support for this - from MMSIM15.1 ISR3 onwards. Not sure what version you're using. I think it's a bit fussy as to what works and what doesn't. My initial attempts didn't work,...
View ArticleRE: Set a permute rule with SKILL
Yes. Depends on what is in the CDF already. If the auLvs simInfo exists already, it would be: cdf=cdfGetBaseCellCDF(ddGetObj("gpdk045" "nmos1v")) cdf->simInfo->auLvs->permuteRule="(p D S)" If...
View ArticleRE: PSS issue when enabling APS multicore simulation
Sounds a bit odd - but I don't think I could diagnose this without seeing more of the setup information. Could you at least post the bottom part of the input.scs - with all the options and analysis...
View ArticleRE: Number of accepted tran steps in spectre log
This is controlled by the transient "annotate" option. It's set in ADE to be "status" which gives you a regular update on the progress of simulation and uses some heuristics to let you know when it's...
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