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3d convas board shape not coming
hi every one In 3d convas 3d viewer board shape not coming exactly. like arcs board cuttings slots. what is problem please help me Thanks, Balaji.j
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RE: vManager API
As an update to this thread, in the last 2 years since the original post, vManager R&D have improved the built-in documentation in the vAPI section of the web portal, including the addition of many...
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Running a SKILL script from Command Line
Hello, I have a skill file that I would like to run in command line. I am looking for the fasting execution time, so "virtuoso -nograph" would be my last resort. What would be the best way to run a...
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RE: Running a SKILL script from Command Line
Hi Karam, dbAccess -load yourCode.il Andrew.
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The Design Infrastructure Alley
One of the new things at DAC this year is the Design Infrastructure Alley. The Alley is an initiative from the ESD Alliance and the Association for High-Performance Computing Professionals to highlight...
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RE: RotateSilkAssyRD.il does not "Center Assembly RDs at Part Origin"
Hello Dave, good day i have use V2.2 skill file . in this skill file text come to the part origin but couldn't rotate. Thanks
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RE: Running a SKILL script from Command Line
Thanks Andrew. I read in a thread that for using sch* commands "virtuoso -nograph" would be unavoidable. Is that true? Is it also the case for mae* commands? Best regards, Karam
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RE: Hierarchical Design using characterized blocks timing issues
Dear Kari, Dimitrios I am also facing issue similar to this. I have two blocks separately implemented using the Encounter. They have huge CTS Global skew and i am unable to balance the CTS of two...
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Create Functional Verilog from Schematic.
Hi, I have a simple schematic with three same AND gates connected together. Each AND gate has also a functional view (obviously the same for all of them) , written in Verilog. What I am trying to...
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RE: Generating Gerber RS274X In 2:3 Format & Gerber File Syntax Issue.
Your 3/5 setting works because 5 is one greater than the resolution you have set (1) meaning 1mil = .0010. My chart which represents only 0 meaning 1mil= .001 database resolution. your setting would...
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RE: Generating Gerber RS274X In 2:3 Format & Gerber File Syntax Issue.
If you had something placed on your board 99.9999. Your format setting needs to be 3/5. Always something greater by one at a minimum. See my comments below for Paul
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RE: Running a SKILL script from Command Line
Hi Karam, Yes and yes. dbAccess only contains the low level database, tech, CDF and SKILL functions - no application layer capabilities. Andrew.
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Remove footprint properties
When creating BGA footprints, we used the package symbol wizard with the default template. These symbols now have several properties that are not in the symbols that we created manually:...
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RE: Create Functional Verilog from Schematic.
I would suggest working through the following Rapid Adoption Kit (RAK) to familiarize yourself with how to create a configuration with the appropriate views....
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Is it Time to Verify Your Chips in the Cloud? Part 1 of 3
Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud. For a while now, there’s been a growing interest in...
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RE: ahdlLib opamp model vref pin
From the code it seems that vref is reference node for output voltage. However, when I run the test Vout doesn't change when vref change over all range. So what is the function of it? This is the nest...
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import spice model to one of the commercial OTA ICS
I've been able to import models using this guide , unfortunately, it doesn't work. The cell view is called OTA and the model file and subcircuit is called LT1228 In particular, I'm trying to import...
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OrCad Capture 16.3: "No signals Present"
When I was trying to edit an older design which my senior had done. When I right click on any Netname, Aliases or Offpage connectors and selecting ' signals ' to see where it is routed it was throwing...
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cannot pass uvm_sequence_item to send_to_dut
Hi all, Problem: I cannot call within uvm_driver the method send_to_dut with uvm_sequence_item. send_to_dut without argument can access class items of uvm_sequence_item , though. My example is based on...
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RE: ahdlLib opamp model vref pin
It's effectively an internal common-mode node; it doesn't have much (if any - I didn't exhaustively check it through) influence on the output (it might if the ibias is large enough, or you're slew rate...
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