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How can you change the waveform viewer defaults to thicker lines and not dotted?
I've looked over a couple previously posted solutions, e.g.: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/34307/default-colors-in-waveform-viewer However I can't seem to...
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RE: How can you change the waveform viewer defaults to thicker lines and not...
Sigh - I spent a while looking for a solution, gave up and then made this post. Then I looked a little more and found the answer 5 minutes later :-/. Here it is:...
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RE: How can you change the waveform viewer defaults to thicker lines and not...
The line style for y0-y9 affects signals (sent from outputs in ADE) so that they cross-probe on the schematic with the same colour and style; for waveforms plotted by other ways, it uses the ViVA...
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RE: How can you change the waveform viewer defaults to thicker lines and not...
Thanks (as always) Andrew.
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RE: detecting process corner from within verilogA model
Thank you, I am following this thread because I need to implement the same and I have a question. I have created a file called "wrapper.scs" which looks exaclty like this: library wrapper section NN...
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RE: Error running Liberate_AMS
There is a work round for this. Look through your models and look for subckt that has a line of "cab ( ) bsource" or higher level model that calls for such subckt. Add it to leaf cell, type can be...
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Cascaded display.drf loading
I have an on-going battle with Virtuoso trying to make things work and/or not look disgusting with everything on a white background (so I can always have WYSIWYG when I print stuff). I made my own...
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RE: Cascaded display.drf loading
More info: I should add that if I go into the Display Resource Editor I can still confirm that align/drawing is still set to red i.e. it doesn't seem to be overwritten. Now I'm really not sure what's...
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RE: How can you change the waveform viewer defaults to thicker lines and not...
Sigh - I thought I had this all locked down, but now that I've gotten out and then back into Virtuoso I'm right back where I started i.e. a waveform viewer with thin dotted lines. I've tried editing...
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Whiteboard Wednesdays - Automotive Sensors: Concepts and Trends
In this week’s Whiteboard Wednesdays video, the second in a three-part series, Robert Schweiger does a deep dive on the technical aspects of the different sensors on a car: camera, radar, and lidar....
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RE: Is there a way to describe the charge across the device as a function of...
You still didn't say which version of spectre you were using. BTW, I was able to upload the file OK when I tried to... Anyway, I think the issue is that the ddt doesn't know the tolerances of the...
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VIVA Table SKILL functions
Hello: I was looking for SKILL functions to work with VIVA tables and so far I have found only a single function. awvTableSignals However this function is very limited. Are there any other functions...
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axlShell does not work
Hi guys, i and trying to add variable in axlshell() but it does not work. anyone can help? This is my code layer = "DRILL" sprintf(s "FORM vf_vis colorview_list Film:%s" layer) axlShell(s) Error msg:...
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Bindkey for raising CIW problem
Hello, First of all, I am quite new to programming in SKILL. I've tried to raise the CIW window by using a bindkey F3 by using this code: procedure(raiseCommandInterpreter() applicationList =...
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RE: How to quickly find device category?
Thanks a lot Andrew! It works for me as I expected.
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RE: detecting process corner from within verilogA model
You can create a parameter in your veriloga model e.g. parameter real getcorner = 1; . Based on the value of of 'getcorner', you can code the functionality in verilogA model using if/else. Then when...
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RE: Bindkey for raising CIW problem
Hi Nicolas, For ADE L you need to explicitly call: hiRegisterBindKeyPrefix("Artist") as described in my article: How to define bindkeys for the ADE L window For me, I tried adding that and then the...
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RE: detecting process corner from within verilogA model
Hi Saloni, thank you for your reply. Implementing the functionality in the verilogA model using the value of the parameter and if/else is clear. My question is how to pass the value from the...
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