Thanks Andrew. I'll suggest that to the parties looking into it. I'm more of an end user waiting at the mercy of the tools guys to get stuff up and running, while wishing I had more ability in that area myself. It feels like we need to (find, then) flip a switch to change the options on what I think is, as of yet, a rather primitive, barely locally developed, out of the box product. As I am currently ignorant on the topic, can you describe briefly the diff between auLvs and auCdl? I have a feeling I can guess that (type of netlisting?), based on your statement. Another mystery 'we' are trying too chase down is (trying to find, and flip an options switch, probably) getting Assura LVS to not ignore dummy devices that are fully tied off. Examples of such devices would be a simple N-channel with source/drain/gate/bulk all tied to ground (or VSS), or a P-channel that has all nodes tied high. I move from place to place frequently, so I get to 'use' varying setups in terms of how teams have tailored their pdk interpretations and local runsets. So, at one place, dummy resistors can be totally ignored in LVS (not my preference), while in another place ANY device in the layout or schem, whether their nodes are tied together or not, must be accounted for. Some folks just don't care about that. Where I'm currently working, these devices are being ignored but we would prefer they not be ignored, and verified instead. Haven't figured out this one yet, though. I'm fairly sure this is simple, but don't know the method with Assura. (In the distant past, I've found and altered lines of code in (non-Cadence) decks where the option was switched.) -Jim![]()
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