Moore's Law is running out of steam. Depending on your point of view, it is dead, dying or slowing. As a result, there is an increasing interest in technologies that go under the title "More than Moore", meaning ways of getting better system integration, performance or cost using approaches other than simply scaling the semiconductor process. Some of these approaches take place on the chip, "scaling boosters" like buried power rails. But this post is looking at technologies above the chip level, mostly innovations in packaging and the implications that this has for system design. History I talked to Cadence's John Park, who told me that he has been doing this sort of heterogeneous integration for 35 years. It used to be called MCM, for multi-chip-module, in the 60s and 70s. The focus was on military and aerospace, with the buzzword being SWAP (Size, Weight, And Power) since a soldier had to carry everything. They were focused on integrating different technologies, and they didn't want to do it at the board level since it was big and heavy. Instead, they did it on a small ceramic module. About ten years ago we started to get system-in-package (SiP) and, especially, RF modules took off, driven by the need for radios in smartphones (Bluetooth, WiFi, and increasingly complex multi-band cellular radios). There was an analog/RF focus so no need for digital tools like timing signoff. Now, and into the future, it is all about heterogeneous integration, including a lot of digital. Everyone is looking to advanced packaging to keep creating more and more complex systems. However, digital SoC doesn't fit the mold of PCB and analog designs that had been sufficient. Now people want to mix process nodes as well as technologies. Advanced Packaging FOWLP sounds like a horrible disease of chickens, but it actually stands for Fan-Out Wafer-Level Packaging. This is a form of packaging where the fanout is created using a traditional IC fabrication process, enabling the device to go directly from the wafer to the PCB. This technology essential skips the traditional packaging step. The Ax chips in recent iPhones use this type of technology. This is one technology that falls under the generic title of "More than Moore." Most people use this term to refer to packaging technologies that allow more complex and higher performance systems to be created without depending just on the scaling of the underlying semiconductor process. FOWLP is actually done by attaching a good die to a wafer and so scaling the approach to handle many die at a time (so the wafer in FOWLP is not the wafer that the chips were manufactured on). The dream is to use flat-panel manufacturing equipment "kick it up a notch" to a much bigger scale. Source: Xilinx But FOWLP is not the only technology like this. Another is interposer-based design, usually called 2.5D. The interposer can actually be silicon, glass, ceramic or organic substrate. This is actually a technology that goes back over 20 years to when we used to call it MCM or multi-chip-modules. The die are flipped and attached to the interposer. The interposer doesn't contain active circuitry, just routing known as RDL (redistribution layer), so it only requires BEOL processing. The die themselves do not need any thru-silicon vias (TSVs), just the interposer. The first commercial product to use this technology were high-end Xilinx arrays, where the big die was instead manufactured as four slices, and more recently where the Serdes was pulled off so that the FPGA slices could be implemented in 16nm but the Serdes remained at 28nm for better analog performance. The diagram above shows the Xilinx approach. Next is true 3D design, where multiple die are stacked on top of each other. All except the bottom die require TSVs to get the signals down the stack. There are obviously some hairy test issues as to how you can test, say, the top die after packaging is complete. High-bandwidth memory (HBM) are die with a standard pattern of TSVs so that they can be stacked with 4 die on top of the memory controller. Stacks like this are available from Samsung, Micron, and perhaps others. Source: AMD These two technologies, 3D and 2.5D, can be combined; for example, putting a GPU onto an interposer along with an HBM stack. The above diagram comes from the AMD keynote at SEMI's SMC (see my post Mark Papermaster: Moore's Law Plus ). The newest technology of all, which seems to be called wafer-on-wafer, is where two wafers containing SoCs (but with no passivation) are joined together, top metal to top metal (presumably with something in between). This allows an SoC twice its size to be fitted into the same area. Connections can be made through the lower chip via TSVs. One slightly specialized technology, but one that has been around for over a decade, is that CMOS image sensors (CIS) for things like cell-phone cameras receive the light through the back of the wafer. After manufacture of the sensor, the wafer is thinned to a few microns, flipped over, and bonded on top of the image processor. The processor can be built in a non-leading-edge technology since it has to be the same size as the sensor; plus CIS is very sensitive to heat, so it is important that the image processor remains cool. System Design Enablement System Design Enablement, or SDE, is Cadence's approach to designing systems, which generally consist of one or more chips, packages, boards and software loads. Obviously, the precise details depend on the system being designed. But when thinking about these "More than Moore" systems, the obvious question is how to design something like this, with multiple die, complex packages, perhaps interposers, probably a board, and almost certainly at least one processor containing a complex software stack. The first step is known as pathfinding. A couple of decades ago, there were very few choices: the process technology was pretty obvious, there might be a choice of ceramic or plastic packages, there was just a single die. Now, the decisions are much more challenging. The type of product (a watch, a hearing aid, a heart pacemaker, a cell phone) influence packaging and chip design. There can be the need to do the floorplan for one chip concurrently with three other chips while simultaneously figuring out the packaging technology, and perhaps an odd PCB form factor (flexible, smartwatches, a circular board in the nose-cone of a plane, and so on). This is the heart of SDE: Cadence enabling the design one part of the system in the context of the rest of the system. Cadence has a tool called OrbitIO for this pathfinding stage. It allows for such tasks as floorplanning an IC, ball-map planning for a package, the top-level design of an interposer, putting the package on a PCB, and so on. But OrbitIO doesn't just allow these tradeoffs to be analyzed, it also has a path to implementation. It can write out the data that is required by the Cadence portfolio of implementation tools: Innovus for digital IC Virtuoso for analog and RF (and sometimes custom digital) SiP Layout advanced IC packaging Allegro PCB (for PCB, obviously) PVS Physical Verification System PCB, Package and Chip Design Tools Advanced packaging is sometimes driven by board and packaging requirements themselves, and a flow-based largely around Allegro is most appropriate since the PCB domain dominates. Alternatively, sometimes the requirements are more driven by the IC domain, and a flow driven by Innovus and Virtuoso is more appropriate, the IC domain dominates. Whichever one is the driver, everything has to work together and iterate so that, for example, package parasitics are correctly analyzed in the IC domain. Increasingly, the flow needs to be even more integrated. For example, being able to do LVS on the entire system and timing signoff end to end. The first step in this direction is Virtuoso System Design Platform, which allows the chip design to be opened in the contact of its environment of package and board. A big gain is being able to LVS to make sure everything is hooked up correctly. One customer had to do a manual check of 8800 connections, and they missed two and ended up with a power-ground short; now it is completely automated and that sort of error cannot slip through. Creating flows that work cleanly with multiple die is not straightforward since they may all have different technologies and so different PDKs. To add to the chips, of course, are all the parasitics associated with the packages and the PCB that they sit on. The World of Chip and Package are Merging It is clear that the world of chip and package are merging, along with interposers, and multi-die designs. Design flows need to combine Virtuoso (chip) and Allegro (package). For example, the AMD chip mentioned above, with a GPU and 4 HBMs was designed that way. Eventually, you need to be able to output all the formats that are required to do the actual manufacturing, gerber for packages and boards, GDS or Oasis for chips. The merge isn't completely seamless yet. For example, to do FOWLP designs, the team will typically start in Virtuoso or Innovus (for analog or digital), take into Allegro to design the RDL layers, and then go back into the chip world for LVS/DRC signoff. There is more standardization than may appear immediately since with the exception of one semiconductor company, every package in the world is designed with Allegro and so the data is available. More Information See the Allegro Package Designer page. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
↧