Set -access +rw for regression

I have an issue where forcing a value on a register works in simulator but not in regression This is how it is done in the testcase. uvm_hdl_deposit("tb_top.dut.infra_i.inst.gen_ing[0].inst.o_ing_pkt_cnt",32'hFFFFFFFF); And the error I get in vManager for regression is Attempting to place a value into tb_top.dut.infra_i.inst.gen_ing[0].inst.o_ing_pkt_cnt which does not have write access. I found someone else on the internet that had a similar problem and solved it by setting -access +rw. I need to know how to set this when running the regression. Should I set it in the testcase? In the vsif? Is it a setting in vManager?Image may be NSFW.
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