For the second year, the Electronic Design Process Symposium (EDPS) took place in Milpitas, having been at Monterey for many years. This was apparently the 25th year EDPS has run. I find EDPS to be a fascinating conference, and I think it is a shame that more people don't attend. Over the years, things I've come across at EDPS include: the first time I heard about RISC-V, long before anyone else seemed to have heard about it (see my post A Raven Has Landed: RISC-V and Chisel ) while I knew about differential power analysis as a side-channel attack on chips, it was at EDPS I actually saw it done: the encryption key was actually read out of a chip using the technique (see my post EDPS Cyber Security Workshop: "Anything Beats Attacking the Crypto Directly" ) even the first time I heard in any detail about David White's work on machine learning in EDA, and we both work for Cadence (see my post EDPS: the Remains of the Day ). In this post I'll summarize what took place this year so that you get a real sense of the breadth of what you missed if you weren't there. I will cover a few of the presentations in their own posts over the coming weeks. Chris Rowen The conference opened with a keynote from Chris Rowen. He's slightly renamed his company to Babblelabs since people were clueless at how to pronounce it with the shorter version of its name. The introduction to Chris's talk was similar to what I covered in Rowen on Vision, Innovation, and the Deep Learning Explosion . One key message is that deep learning silicon is easy: compute is dominated by multiply-add (or MAC). The coefficients (weights) are read-only and heavily re-used. The memory pattern is static and regular and so caches are not required. Programmability means that the same fabric can be used for many applications such as both image recognition and voice recognition. On the other hand, deep learning silicon is also hard. There are impediments to efficiency such as mixed convolution sizes, non-unit strides, difficult parallelization, optimizing sparsity. Memory bandwidth is a challenge since models are large (10+ megabytes), fully connected layers are hard to optimize with each coefficient used once, and complex inter-layer connectivity. The whole chain, from the standard frameworks like Caffe and Tensorflow all the way down to the silicon, needs to be optimized. Chris thinks that silicon availability is getting ahead of deployable applications, leading to chips being a solution looking for a (valuable) problem. Chris wrapped up talking about deep learning startups, of which there are many. As he quipped, an AI startup is "any startup founded in the last three years". I think a deep learning silicon startup is any silicon startup over the period. He had a graph (above) giving a taxonomy of what silicon is where on the edge inference to cloud acceleration axis, and the general purpose processor to deep learning specific. Patrick Groeneveld The program proper opened with Cadence's Patrick Groeneveld talking about a course that he had run at Stanford (along with Antun Domic and Raúl Camposano (that is a lot of years of EDA experience) called EE292A Electronic Design Automation (EDA) and Machine Learning Hardware. I will cover that in its own post . Deep Learning The rest of the morning was taken up with various facets of deep learning. The presenters were: Balachandran Ranejendran of Dell EMC on Machine Learning in System Design and EDA Rohit Sharma of Fiarpath on Exploring Machine Learning for EDA Joonyoung Kim of NVXL on Design Flow for Machine Learning FPGA Jai Kumar of Intel on Efficient HW/SW Co-Design of Complex Emerging Systems Andrew Kahng The afternoon kicked off with Andrew's keynote Driving, Driven, Along for the Ride: Evolutions of EDA, Manufacturing and Design . Even back in 2001, the ITRS roadmap called out "cost of design is the greatest threat to the continuation of the semiconductor roadmap." Andrew's presentation was about who is going to drive EDA going forward: EDA itself, or everyone else? Or is EDA just along for the ride, as in the title. I'll cover Andrew's talk in a separate post. Smart Manufacturing, System Reliability The first part of that afternoon was taken up with presentations on smart manufacturing: Tom Salmon of SEMI (going for the winner of the longest title) on Smart Manufacturing: Convergence, Co-Design, and Co-Optimization Improve Performance, Sustainability, and Yield A cross Microelectronic Supply Chains Willfried Bier or NextFlex on Flexible Hybrid Electronics: New Challenges , New Opportunities Mark Knowles of Mentor (runner-up for the longest title) on Connecting Advanced Manufacturing Test to Design, Fab, and Final Product Yield for Complex FinFET Defect Challenges Dave Armstong of Advantest on Device Manufacturing in an Era of Neural Networks The second half of the afternoon was presentations on system reliability for ADAS, 5G, AI, and photonics: Di Liang of HP Labs on Integrated Photonic Interconnect Reliability for Datacom Applications Amisha Sheth of Intel on 5G Validation Process and Challenges Ritesh Tyagi of Infineon on Functional Safety Architecture Challenges to Achieve Failsafe Operation in ADAS and AD Applications Norman Chang of ANSYS on Achieving 5G-ADAS-AI Reliability for Advanced FinFET Designs ESD Alliance Hogan Evening That evening was a "keynote" co-organized with the ESD Alliance in which Jim Hogan interviewed Amit Gupta on his keys for crossing the chasm and success in an EDA startup. I wasn't able to attend, although I've talked to Amit about this before, see my post Crossing the Chasm: Hogan Interviews Amit Gupta . I don't want to take anything away from Amit's success with two startups based in Saskatoon, but part of his recipe doesn't generalize that well. Locate in a desolate part of Canada, get subsidies from the Canadian government, have basically zero turnover since there's nowhere else locally, and so on. If you are in in Silicon Valley, this advice is a bit like that old joke where a driver asks a local farmer for directions (this is pre GPS obviously) and gets told "if I were you, I wouldn't start from here." Confidential Cloud What is this building? The new Apple Campus in Cupertino? Actually, it is GCHQ in Cheltenham England, roughly the UK equivalent of the NSA. That is where the second day's keynote speaker, Simon Johnson, worked for many years. After 9/11, the US basically said that to continue to be part of the visa waiver program, where citizens don't need to go to the US embassy every time they want to visit the US, passports would have to be biometric and machine-readable. He worked on that biometric passport program "and some other stuff I can't talk about." Today, he is at Inteo working in their security platform division. He talked about Confidential Cloud, which is the idea of building applications in the cloud where even the cloud service provider does not need to be trusted. I will cover that in a separate post. Security The rest of the morning was taken up with various presentations on security: Gong Qu of ISR on Polymorphic Gates and Their Applications in Hardware Security Alessandra Nardi of Cadence on Functional Safety for Semiconductor Designs Ujjwal Guin of Auburn University on Cybersecurity Solutions in Hardware Blockchain The last presentation of the morning session was by Naresh Sehgal of Intel on Introduction to Blockchain and Its Potential Applications in EDA . This was followed (after lunch) by a panel session on BlockChain: Will it Work for IoT Security? although most of the discussion was on other blockchain topics. The panelists were Jim Hogan (who has invested in some blockchain companies), Naresh back to be on the panel, who has been digging into blockchain while on his sabbatical from Intel, and James Gambale, who is a chief engineer of Loomasoft Corp (and was, for many years, a patent attorney at Qualcomm). My experience with discussions on blockchain, and this was no different, was that people mix up some application (such as keeping track of IP usage throughout the design and manufacturing flow) with the underlying technology. Blockchain is sexy and so that rubs off onto whatever you are talking about. I think VCs are irrationally keen on it since it doesn't have an elephant like Google or Facebook sitting there already, so if it does become something big, there is the possibility of being "the Google of blockchain". But mostly it still seems to be a solution chasing a problem. For example, for the problem of helping the DoD keep track of IP used in their devices over the multi-decade lifecycle of the typical defense product, why would you use an unwieldy expensive technology like blockchain to hold a modestly sized, low activity, database that the DoD could perfectly well centralize on a single server (or in the cloud for more redundancy). Digital Marketing 2.0 In the same room at SEMI where EDPS was held will be the second ESD Alliance digital marketing workshop, with Nicolas Athanasopoulos of OneSpin. I wrote three posts about the previous workshop (if you want to read them, then start with the first one Digital Marketing in EDA...With No Hands on the Wheel ). It is $30 for anyone who works for an ESD Alliance member company (and that includes dinner). It is on October 3rd, with dinner at 6pm and the workshop proper starting at 7pm. Yes, it is also TSMC's OIP symposium that day, so not the best choice of evening since a lot of EDA marketing folk will be in the Santa Clara Convention Center all day. More details, including registration, are on the ESD Alliance website . I'll see you there. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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