The new release of the Virtuoso platform (*ICADVM18.1) offers groundbreaking analysis capabilities and an innovational new simulation-driven layout for more robust and efficient design implementation as well as extending our support for the most advanced process technologies. With this solution, we are able to significantly improve productivity through advanced methodologies and provide the most comprehensive set of solutions in the industry with an interoperable flow across chip, package, module and board. *This feature will also be available in IC6.1.8 for mature nodes. You spoke and we listened. You wanted a system to aid the communication between schematic and layout designers, who are often situated in different buildings, countries, or time zones. Where design goals can be defined and discussed, implementation restrictions resolved, and decisions agreed and recorded to prevent duplication of effort during design reuse. Cadence brings you… Virtuoso Design Intent, a new capability to complement the Virtuoso Schematic Editor XL and Virtuoso Layout Suite XL applications. Liberating designers Virtuoso Design Intent facilitates and captures the communication between the schematic designer specifying design goals and the layout designer implementing and achieving those goals. Schematic designers focus on capturing their design intent without having to create physical constraints on the design. This doesn’t mean farewell to Virtuoso Unified Custom Constraints; instead layout designers now have the freedom to decide how to physically implement and achieve the design intent. Read on to discover a little more about Virtuoso Design Intent and we will return to how it complements the constraints flow. The Design Intent flow The flow of Virtuoso Design Intent is contained within Schematics XL and Layout XL and requires interaction between the schematic and layout designers for a design. Schematic designer selects an object or group of objects to have a design intent added (e.g. device matching requirements, noisy/sensitive nets, high currents, voltage drops, pin information). They capture their design goals on the Create Design Intent form using a combination of text notes and predefined property profiles, which contain frequently used design intent specific properties that formalize their design goals e.g. add shield, add guard ring, and so on. Each design intent is stored in the schematic and is displayed as an easily identifiable, colored annotation on the canvas. The created design intents are transferred (synced) to Virtuoso Layout XL and from then on design intent changes are updated on the design, visible in both Schematics XL and Layout XL. Layout designers can clearly identify the objects specified with design intents and begin implementing each intent. Using the Edit Design Intent form, they can update the current implementation stage and add implementation notes or queries to communicate back to the schematic designer. By regularly syncing, the schematic designer is updated on the implementation progress of each design intent in the design. Via the Edit Design Intent form, they can respond to any queries or comments recorded by the layout designer, adapting the intent if required and ultimately signing off on the implementation of their design intent. Progress of all the design intent implementation on a design can be checked at any point using a high-level summary report generated from either Schematics XL or Layout XL. What about the existing Virtuoso Unified Custom Constraints flow? If you are familiar with Virtuoso Unified Custom Constraints, our interactive and automated constraint-driven tool, you’ll be aware that it assists you in creating error free designs across the Schematics XL and Layout XL applications. Each constraint on a design is a physical or electrical rule defined by you to help you achieve your design goals. Virtuoso Design Intent complements the existing Constraints flows by capturing the schematic designer’s requirements at a higher level, enabling them to communicate their requirements to layout engineers without overlapping their roles. By using Virtuoso Design Intent to capture design goals, Constraints can be used to focus purely on defining the specific rules that are required to satisfy and implement the designer’s original intent. Sound good? It looks even better… Watch out for our upcoming Virtuoso platform ICADVM18.1 and IC6.1.8 releases. Contact Us For more information on What’s New in Virtuoso ICADVM18.1 and IC6.1.8 releases, see What's New in Virtuoso . For more information on Cadence Custom IC/Analog/RF Design products and solutions, visit www.cadence.com . For more information on the New Virtuoso Design Platform, or if you have any questions or feedback on the features covered in this blog, please contact team_virtuoso@cadence.com . If you would like to receive similar updates about what new and exciting features are being built into Virtuoso for our upcoming Advanced Nodes and Advanced Methodologies releases, enter your email ID in the Subscriptions field at the top of the page and click SUBSCRIBE NOW. Sarah Finlayson, Gautam Kumar and Mark Baker![]()
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