PVS LVS reporting missing pins in Layout

I have done the layout of a cell and included all the pins that were in the schematic by using "generate selected from source" for each one of them and choosing the appropriate pin layer. The "connectivity -> check --> against source" and "connectivity--> update --> components and nets" validates that the pins have bee placed. DRC with PVS is clean. Running LVS with PVS results in mismatch showing all pins are missing in layout.