Dear Andrew, thank you very much for your answer. It works perfectly. If I may, I'd like to ask you another question related to table_model. Do you know what is the algorithm behind this function ? I would like to know if the table model loads the entire table once or if it access the file everytime I ask for it ? I ask this because my simulation time is quite long compared to transistor level (spectre) simulation... The design is small, around 30 transistors (65nm). schematic level takes around 200ms, verilog-wreal with table 4s... thank you for your answer. OL
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