Hi, thanks for your reply Guang. This is how my template for the inverter looks like : https://pastebin.com/1gYJHUP7 As per the reference manual, I use the default modes (haven't specified them explicitly) for voltage_map, leakage_mode and leakage_add_input_pin in above template. So that means, I am using following settings (1) for the leakage computation : But when I simulate this inverter schematic with parasitics in AE, the observed leakage power (IDDxVDD) when the input=1 (PMOS off) was 95.95 pW (87pA*1.1V). When the input=0 (NMOS off), this was found to be 190.01 pW (172.74 pA * 1.1V). But non of the leakage power values in the generated .lib file ( https://pastebin.com/grfasa1s ) for given input conditions do not match to these simulation values. Am I missing something here ? Anuradha![]()
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