Using a Tensilica core, we have 12 external interrupts defined, 6 edge/6 level. We have C-based ISRs for each interrupt source. We register the ISR with "_xtos_set_interrupt_handler_arg" function call. We can observe the ISRs being taken when the interrupt happens, the code inside ISR executes for sure. However, inside the ISR, we are reading the INTERRUPT register through: rdata = xthal_get_interrupt(); Now, for level interrupts, this function call returns the expected interrupt bit that caused the interrupt. For edge type interrupts, this function returns 0. From the documentation, what I see is that, for level interrupts the corresponding INTERRUPT register bit is set/cleared by the external logic driving the BInterrupt bit. For edge interrupts, the status should be latched by the CPU and kept in INTERRUPT register until it is cleared by SW. Any idea why I'm reading 0x0 from INTERRUPT register for edge interrupts?Image may be NSFW.
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