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RE: Schematic Extraction of Standard Cells of TSMC 40nm and AMS

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Hi Anuradha, If you create the symbols for std cells in a library, you can then point to the corresponding verilog files as a command-line argument to your AMS simulation. Here's a Rapid Adoption Kit on AMS flow: https://support.cadence.com/apex/articleattachmentportal?id=a1O0V000007MnZlUAK&pageName=ArticleContent&attachId=0690V000003xwUGQAY&sq=005d0000001T4VEAA0_201852211126632 In this example, there is a cell called 'inv'. If you didn't have a verilog view for this cell, the config view will choose symbol as the stop view. When you run AMS simulation from ADE, you can provide the *.v files for standard cells. On the same lines, instead of providing *.v files to irun, you can use -makelib and -reflib options. Using -makelib, you can compile all std cell *.v files once into a user-defined library. Then, in all subsequent simulations, you can point to this compiled library using -reflib argument. This method is well documented, but if you need any further help, please tell me the IC and INCISIVE version you are using so I can share the correct tool snapshots with you. Regards Saloni

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