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RE: Verilog A ADC design

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I selected the 10 signals d0 to d9 and then did (in the ViVA graph) Measurements->Analog to Digital. I specified the mid-value for the threshold, and made sure that the "Make Bus" was checked. If the bits are in the wrong order (MSB->LSB) then you can fix this by clicking on the Signal/Expr Names column heading to reverse the sort. You can control the radix and give a name for the bus - and then it adds the bus to the output. Hopefully that's clear enough without me posting a picture of the form. Regards, Andrew.

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