RE: Convert schematic to Verilog file

Is it possible to split instance names? for example, there is instace in the verilog that we get by NC Verilog netlist generation from a schematic BFHVTX12 buffer[1:0] ( .Z(cml_sc[1:0]), .A(buf_cml_sc_i[1:0])); but we need to have: BFHVTX12 buffer_1 ( .Z(cml_sc[1]), .A(buf_cml_sc_i[1])); BFHVTX12 buffer_0 ( .Z(cml_sc[0]), .A(buf_cml_sc_i[0])); Then we send verilog netlist to Encounter. Encounter does not understand instance name "buffer[1:0]" basically, there are a lot of instance like that. We always have to split it manually.